1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2 //
3 // This file is provided under a dual BSD/GPLv2 license. When using or
4 // redistributing this file, you may do so under either license.
5 //
6 // Copyright(c) 2018 Intel Corporation. All rights reserved.
7 //
8 // Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
9 //
10
11 /*
12 * Hardware interface for audio DSP on Baytrail, Braswell and Cherrytrail.
13 */
14
15 #include <linux/module.h>
16 #include <sound/sof.h>
17 #include <sound/sof/xtensa.h>
18 #include <sound/soc-acpi.h>
19 #include <sound/soc-acpi-intel-match.h>
20 #include <sound/intel-dsp-config.h>
21 #include "../ops.h"
22 #include "atom.h"
23 #include "shim.h"
24 #include "../sof-acpi-dev.h"
25 #include "../sof-audio.h"
26 #include "../../intel/common/soc-intel-quirks.h"
27
28 static const struct snd_sof_debugfs_map byt_debugfs[] = {
29 {"dmac0", DSP_BAR, DMAC0_OFFSET, DMAC_SIZE,
30 SOF_DEBUGFS_ACCESS_ALWAYS},
31 {"dmac1", DSP_BAR, DMAC1_OFFSET, DMAC_SIZE,
32 SOF_DEBUGFS_ACCESS_ALWAYS},
33 {"ssp0", DSP_BAR, SSP0_OFFSET, SSP_SIZE,
34 SOF_DEBUGFS_ACCESS_ALWAYS},
35 {"ssp1", DSP_BAR, SSP1_OFFSET, SSP_SIZE,
36 SOF_DEBUGFS_ACCESS_ALWAYS},
37 {"ssp2", DSP_BAR, SSP2_OFFSET, SSP_SIZE,
38 SOF_DEBUGFS_ACCESS_ALWAYS},
39 {"iram", DSP_BAR, IRAM_OFFSET, IRAM_SIZE,
40 SOF_DEBUGFS_ACCESS_D0_ONLY},
41 {"dram", DSP_BAR, DRAM_OFFSET, DRAM_SIZE,
42 SOF_DEBUGFS_ACCESS_D0_ONLY},
43 {"shim", DSP_BAR, SHIM_OFFSET, SHIM_SIZE_BYT,
44 SOF_DEBUGFS_ACCESS_ALWAYS},
45 };
46
47 static const struct snd_sof_debugfs_map cht_debugfs[] = {
48 {"dmac0", DSP_BAR, DMAC0_OFFSET, DMAC_SIZE,
49 SOF_DEBUGFS_ACCESS_ALWAYS},
50 {"dmac1", DSP_BAR, DMAC1_OFFSET, DMAC_SIZE,
51 SOF_DEBUGFS_ACCESS_ALWAYS},
52 {"dmac2", DSP_BAR, DMAC2_OFFSET, DMAC_SIZE,
53 SOF_DEBUGFS_ACCESS_ALWAYS},
54 {"ssp0", DSP_BAR, SSP0_OFFSET, SSP_SIZE,
55 SOF_DEBUGFS_ACCESS_ALWAYS},
56 {"ssp1", DSP_BAR, SSP1_OFFSET, SSP_SIZE,
57 SOF_DEBUGFS_ACCESS_ALWAYS},
58 {"ssp2", DSP_BAR, SSP2_OFFSET, SSP_SIZE,
59 SOF_DEBUGFS_ACCESS_ALWAYS},
60 {"ssp3", DSP_BAR, SSP3_OFFSET, SSP_SIZE,
61 SOF_DEBUGFS_ACCESS_ALWAYS},
62 {"ssp4", DSP_BAR, SSP4_OFFSET, SSP_SIZE,
63 SOF_DEBUGFS_ACCESS_ALWAYS},
64 {"ssp5", DSP_BAR, SSP5_OFFSET, SSP_SIZE,
65 SOF_DEBUGFS_ACCESS_ALWAYS},
66 {"iram", DSP_BAR, IRAM_OFFSET, IRAM_SIZE,
67 SOF_DEBUGFS_ACCESS_D0_ONLY},
68 {"dram", DSP_BAR, DRAM_OFFSET, DRAM_SIZE,
69 SOF_DEBUGFS_ACCESS_D0_ONLY},
70 {"shim", DSP_BAR, SHIM_OFFSET, SHIM_SIZE_CHT,
71 SOF_DEBUGFS_ACCESS_ALWAYS},
72 };
73
byt_reset_dsp_disable_int(struct snd_sof_dev * sdev)74 static void byt_reset_dsp_disable_int(struct snd_sof_dev *sdev)
75 {
76 /* Disable Interrupt from both sides */
77 snd_sof_dsp_update_bits64(sdev, DSP_BAR, SHIM_IMRX, 0x3, 0x3);
78 snd_sof_dsp_update_bits64(sdev, DSP_BAR, SHIM_IMRD, 0x3, 0x3);
79
80 /* Put DSP into reset, set reset vector */
81 snd_sof_dsp_update_bits64(sdev, DSP_BAR, SHIM_CSR,
82 SHIM_BYT_CSR_RST | SHIM_BYT_CSR_VECTOR_SEL,
83 SHIM_BYT_CSR_RST | SHIM_BYT_CSR_VECTOR_SEL);
84 }
85
byt_suspend(struct snd_sof_dev * sdev,u32 target_state)86 static int byt_suspend(struct snd_sof_dev *sdev, u32 target_state)
87 {
88 byt_reset_dsp_disable_int(sdev);
89
90 return 0;
91 }
92
byt_resume(struct snd_sof_dev * sdev)93 static int byt_resume(struct snd_sof_dev *sdev)
94 {
95 /* enable BUSY and disable DONE Interrupt by default */
96 snd_sof_dsp_update_bits64(sdev, DSP_BAR, SHIM_IMRX,
97 SHIM_IMRX_BUSY | SHIM_IMRX_DONE,
98 SHIM_IMRX_DONE);
99
100 return 0;
101 }
102
byt_remove(struct snd_sof_dev * sdev)103 static int byt_remove(struct snd_sof_dev *sdev)
104 {
105 byt_reset_dsp_disable_int(sdev);
106
107 return 0;
108 }
109
byt_acpi_probe(struct snd_sof_dev * sdev)110 static int byt_acpi_probe(struct snd_sof_dev *sdev)
111 {
112 struct snd_sof_pdata *pdata = sdev->pdata;
113 const struct sof_dev_desc *desc = pdata->desc;
114 struct platform_device *pdev =
115 container_of(sdev->dev, struct platform_device, dev);
116 struct resource *mmio;
117 u32 base, size;
118 int ret;
119
120 /* DSP DMA can only access low 31 bits of host memory */
121 ret = dma_coerce_mask_and_coherent(sdev->dev, DMA_BIT_MASK(31));
122 if (ret < 0) {
123 dev_err(sdev->dev, "error: failed to set DMA mask %d\n", ret);
124 return ret;
125 }
126
127 /* LPE base */
128 mmio = platform_get_resource(pdev, IORESOURCE_MEM,
129 desc->resindex_lpe_base);
130 if (mmio) {
131 base = mmio->start;
132 size = resource_size(mmio);
133 } else {
134 dev_err(sdev->dev, "error: failed to get LPE base at idx %d\n",
135 desc->resindex_lpe_base);
136 return -EINVAL;
137 }
138
139 dev_dbg(sdev->dev, "LPE PHY base at 0x%x size 0x%x", base, size);
140 sdev->bar[DSP_BAR] = devm_ioremap(sdev->dev, base, size);
141 if (!sdev->bar[DSP_BAR]) {
142 dev_err(sdev->dev, "error: failed to ioremap LPE base 0x%x size 0x%x\n",
143 base, size);
144 return -ENODEV;
145 }
146 dev_dbg(sdev->dev, "LPE VADDR %p\n", sdev->bar[DSP_BAR]);
147
148 /* TODO: add offsets */
149 sdev->mmio_bar = DSP_BAR;
150 sdev->mailbox_bar = DSP_BAR;
151
152 /* IMR base - optional */
153 if (desc->resindex_imr_base == -1)
154 goto irq;
155
156 mmio = platform_get_resource(pdev, IORESOURCE_MEM,
157 desc->resindex_imr_base);
158 if (mmio) {
159 base = mmio->start;
160 size = resource_size(mmio);
161 } else {
162 dev_err(sdev->dev, "error: failed to get IMR base at idx %d\n",
163 desc->resindex_imr_base);
164 return -ENODEV;
165 }
166
167 /* some BIOSes don't map IMR */
168 if (base == 0x55aa55aa || base == 0x0) {
169 dev_info(sdev->dev, "IMR not set by BIOS. Ignoring\n");
170 goto irq;
171 }
172
173 dev_dbg(sdev->dev, "IMR base at 0x%x size 0x%x", base, size);
174 sdev->bar[IMR_BAR] = devm_ioremap(sdev->dev, base, size);
175 if (!sdev->bar[IMR_BAR]) {
176 dev_err(sdev->dev, "error: failed to ioremap IMR base 0x%x size 0x%x\n",
177 base, size);
178 return -ENODEV;
179 }
180 dev_dbg(sdev->dev, "IMR VADDR %p\n", sdev->bar[IMR_BAR]);
181
182 irq:
183 /* register our IRQ */
184 sdev->ipc_irq = platform_get_irq(pdev, desc->irqindex_host_ipc);
185 if (sdev->ipc_irq < 0)
186 return sdev->ipc_irq;
187
188 dev_dbg(sdev->dev, "using IRQ %d\n", sdev->ipc_irq);
189 ret = devm_request_threaded_irq(sdev->dev, sdev->ipc_irq,
190 atom_irq_handler, atom_irq_thread,
191 IRQF_SHARED, "AudioDSP", sdev);
192 if (ret < 0) {
193 dev_err(sdev->dev, "error: failed to register IRQ %d\n",
194 sdev->ipc_irq);
195 return ret;
196 }
197
198 /* enable BUSY and disable DONE Interrupt by default */
199 snd_sof_dsp_update_bits64(sdev, DSP_BAR, SHIM_IMRX,
200 SHIM_IMRX_BUSY | SHIM_IMRX_DONE,
201 SHIM_IMRX_DONE);
202
203 /* set default mailbox offset for FW ready message */
204 sdev->dsp_box.offset = MBOX_OFFSET;
205
206 return ret;
207 }
208
209 /* baytrail ops */
210 static const struct snd_sof_dsp_ops sof_byt_ops = {
211 /* device init */
212 .probe = byt_acpi_probe,
213 .remove = byt_remove,
214
215 /* DSP core boot / reset */
216 .run = atom_run,
217 .reset = atom_reset,
218
219 /* Register IO */
220 .write = sof_io_write,
221 .read = sof_io_read,
222 .write64 = sof_io_write64,
223 .read64 = sof_io_read64,
224
225 /* Block IO */
226 .block_read = sof_block_read,
227 .block_write = sof_block_write,
228
229 /* Mailbox IO */
230 .mailbox_read = sof_mailbox_read,
231 .mailbox_write = sof_mailbox_write,
232
233 /* doorbell */
234 .irq_handler = atom_irq_handler,
235 .irq_thread = atom_irq_thread,
236
237 /* ipc */
238 .send_msg = atom_send_msg,
239 .fw_ready = sof_fw_ready,
240 .get_mailbox_offset = atom_get_mailbox_offset,
241 .get_window_offset = atom_get_window_offset,
242
243 .ipc_msg_data = sof_ipc_msg_data,
244 .ipc_pcm_params = sof_ipc_pcm_params,
245
246 /* machine driver */
247 .machine_select = atom_machine_select,
248 .machine_register = sof_machine_register,
249 .machine_unregister = sof_machine_unregister,
250 .set_mach_params = atom_set_mach_params,
251
252 /* debug */
253 .debug_map = byt_debugfs,
254 .debug_map_count = ARRAY_SIZE(byt_debugfs),
255 .dbg_dump = atom_dump,
256 .debugfs_add_region_item = snd_sof_debugfs_add_region_item_iomem,
257
258 /* stream callbacks */
259 .pcm_open = sof_stream_pcm_open,
260 .pcm_close = sof_stream_pcm_close,
261
262 /* module loading */
263 .load_module = snd_sof_parse_module_memcpy,
264
265 /*Firmware loading */
266 .load_firmware = snd_sof_load_firmware_memcpy,
267
268 /* PM */
269 .suspend = byt_suspend,
270 .resume = byt_resume,
271
272 /* DAI drivers */
273 .drv = atom_dai,
274 .num_drv = 3, /* we have only 3 SSPs on byt*/
275
276 /* ALSA HW info flags */
277 .hw_info = SNDRV_PCM_INFO_MMAP |
278 SNDRV_PCM_INFO_MMAP_VALID |
279 SNDRV_PCM_INFO_INTERLEAVED |
280 SNDRV_PCM_INFO_PAUSE |
281 SNDRV_PCM_INFO_BATCH,
282
283 .dsp_arch_ops = &sof_xtensa_arch_ops,
284 };
285
286 static const struct sof_intel_dsp_desc byt_chip_info = {
287 .cores_num = 1,
288 .host_managed_cores_mask = 1,
289 };
290
291 /* cherrytrail and braswell ops */
292 static const struct snd_sof_dsp_ops sof_cht_ops = {
293 /* device init */
294 .probe = byt_acpi_probe,
295 .remove = byt_remove,
296
297 /* DSP core boot / reset */
298 .run = atom_run,
299 .reset = atom_reset,
300
301 /* Register IO */
302 .write = sof_io_write,
303 .read = sof_io_read,
304 .write64 = sof_io_write64,
305 .read64 = sof_io_read64,
306
307 /* Block IO */
308 .block_read = sof_block_read,
309 .block_write = sof_block_write,
310
311 /* Mailbox IO */
312 .mailbox_read = sof_mailbox_read,
313 .mailbox_write = sof_mailbox_write,
314
315 /* doorbell */
316 .irq_handler = atom_irq_handler,
317 .irq_thread = atom_irq_thread,
318
319 /* ipc */
320 .send_msg = atom_send_msg,
321 .fw_ready = sof_fw_ready,
322 .get_mailbox_offset = atom_get_mailbox_offset,
323 .get_window_offset = atom_get_window_offset,
324
325 .ipc_msg_data = sof_ipc_msg_data,
326 .ipc_pcm_params = sof_ipc_pcm_params,
327
328 /* machine driver */
329 .machine_select = atom_machine_select,
330 .machine_register = sof_machine_register,
331 .machine_unregister = sof_machine_unregister,
332 .set_mach_params = atom_set_mach_params,
333
334 /* debug */
335 .debug_map = cht_debugfs,
336 .debug_map_count = ARRAY_SIZE(cht_debugfs),
337 .dbg_dump = atom_dump,
338 .debugfs_add_region_item = snd_sof_debugfs_add_region_item_iomem,
339
340 /* stream callbacks */
341 .pcm_open = sof_stream_pcm_open,
342 .pcm_close = sof_stream_pcm_close,
343
344 /* module loading */
345 .load_module = snd_sof_parse_module_memcpy,
346
347 /*Firmware loading */
348 .load_firmware = snd_sof_load_firmware_memcpy,
349
350 /* PM */
351 .suspend = byt_suspend,
352 .resume = byt_resume,
353
354 /* DAI drivers */
355 .drv = atom_dai,
356 /* all 6 SSPs may be available for cherrytrail */
357 .num_drv = 6,
358
359 /* ALSA HW info flags */
360 .hw_info = SNDRV_PCM_INFO_MMAP |
361 SNDRV_PCM_INFO_MMAP_VALID |
362 SNDRV_PCM_INFO_INTERLEAVED |
363 SNDRV_PCM_INFO_PAUSE |
364 SNDRV_PCM_INFO_BATCH,
365
366 .dsp_arch_ops = &sof_xtensa_arch_ops,
367 };
368
369 static const struct sof_intel_dsp_desc cht_chip_info = {
370 .cores_num = 1,
371 .host_managed_cores_mask = 1,
372 };
373
374 /* BYTCR uses different IRQ index */
375 static const struct sof_dev_desc sof_acpi_baytrailcr_desc = {
376 .machines = snd_soc_acpi_intel_baytrail_machines,
377 .resindex_lpe_base = 0,
378 .resindex_pcicfg_base = 1,
379 .resindex_imr_base = 2,
380 .irqindex_host_ipc = 0,
381 .chip_info = &byt_chip_info,
382 .default_fw_path = "intel/sof",
383 .default_tplg_path = "intel/sof-tplg",
384 .default_fw_filename = "sof-byt.ri",
385 .nocodec_tplg_filename = "sof-byt-nocodec.tplg",
386 .ops = &sof_byt_ops,
387 };
388
389 static const struct sof_dev_desc sof_acpi_baytrail_desc = {
390 .machines = snd_soc_acpi_intel_baytrail_machines,
391 .resindex_lpe_base = 0,
392 .resindex_pcicfg_base = 1,
393 .resindex_imr_base = 2,
394 .irqindex_host_ipc = 5,
395 .chip_info = &byt_chip_info,
396 .default_fw_path = "intel/sof",
397 .default_tplg_path = "intel/sof-tplg",
398 .default_fw_filename = "sof-byt.ri",
399 .nocodec_tplg_filename = "sof-byt-nocodec.tplg",
400 .ops = &sof_byt_ops,
401 };
402
403 static const struct sof_dev_desc sof_acpi_cherrytrail_desc = {
404 .machines = snd_soc_acpi_intel_cherrytrail_machines,
405 .resindex_lpe_base = 0,
406 .resindex_pcicfg_base = 1,
407 .resindex_imr_base = 2,
408 .irqindex_host_ipc = 5,
409 .chip_info = &cht_chip_info,
410 .default_fw_path = "intel/sof",
411 .default_tplg_path = "intel/sof-tplg",
412 .default_fw_filename = "sof-cht.ri",
413 .nocodec_tplg_filename = "sof-cht-nocodec.tplg",
414 .ops = &sof_cht_ops,
415 };
416
417 static const struct acpi_device_id sof_baytrail_match[] = {
418 { "80860F28", (unsigned long)&sof_acpi_baytrail_desc },
419 { "808622A8", (unsigned long)&sof_acpi_cherrytrail_desc },
420 { }
421 };
422 MODULE_DEVICE_TABLE(acpi, sof_baytrail_match);
423
sof_baytrail_probe(struct platform_device * pdev)424 static int sof_baytrail_probe(struct platform_device *pdev)
425 {
426 struct device *dev = &pdev->dev;
427 const struct sof_dev_desc *desc;
428 const struct acpi_device_id *id;
429 int ret;
430
431 id = acpi_match_device(dev->driver->acpi_match_table, dev);
432 if (!id)
433 return -ENODEV;
434
435 ret = snd_intel_acpi_dsp_driver_probe(dev, id->id);
436 if (ret != SND_INTEL_DSP_DRIVER_ANY && ret != SND_INTEL_DSP_DRIVER_SOF) {
437 dev_dbg(dev, "SOF ACPI driver not selected, aborting probe\n");
438 return -ENODEV;
439 }
440
441 desc = device_get_match_data(&pdev->dev);
442 if (!desc)
443 return -ENODEV;
444
445 if (desc == &sof_acpi_baytrail_desc && soc_intel_is_byt_cr(pdev))
446 desc = &sof_acpi_baytrailcr_desc;
447
448 return sof_acpi_probe(pdev, desc);
449 }
450
451 /* acpi_driver definition */
452 static struct platform_driver snd_sof_acpi_intel_byt_driver = {
453 .probe = sof_baytrail_probe,
454 .remove = sof_acpi_remove,
455 .driver = {
456 .name = "sof-audio-acpi-intel-byt",
457 .pm = &sof_acpi_pm,
458 .acpi_match_table = sof_baytrail_match,
459 },
460 };
461 module_platform_driver(snd_sof_acpi_intel_byt_driver);
462
463 MODULE_LICENSE("Dual BSD/GPL");
464 MODULE_IMPORT_NS(SND_SOC_SOF_INTEL_HIFI_EP_IPC);
465 MODULE_IMPORT_NS(SND_SOC_SOF_XTENSA);
466 MODULE_IMPORT_NS(SND_SOC_SOF_ACPI_DEV);
467 MODULE_IMPORT_NS(SND_SOC_SOF_INTEL_ATOM_HIFI_EP);
468