Searched refs:ADF_CSR_RD (Results 1 – 11 of 11) sorted by relevance
| /linux/drivers/crypto/qat/qat_common/ |
| A D | adf_gen2_hw_data.c | 20 errsou3 = ADF_CSR_RD(pmisc_addr, ADF_GEN2_ERRSOU3); in adf_gen2_get_vf2pf_sources()
26 errmsk3 = ADF_CSR_RD(pmisc_addr, ADF_GEN2_ERRMSK3); in adf_gen2_get_vf2pf_sources()
37 u32 val = ADF_CSR_RD(pmisc_addr, ADF_GEN2_ERRMSK3) in adf_gen2_enable_vf2pf_interrupts()
48 u32 val = ADF_CSR_RD(pmisc_addr, ADF_GEN2_ERRMSK3) in adf_gen2_disable_vf2pf_interrupts()
85 val = ADF_CSR_RD(csr, ADF_GEN2_AE_CTX_ENABLES(i)); in adf_gen2_enable_error_correction()
88 val = ADF_CSR_RD(csr, ADF_GEN2_AE_MISC_CONTROL(i)); in adf_gen2_enable_error_correction()
95 val = ADF_CSR_RD(csr, ADF_GEN2_UERRSSMSH(i)); in adf_gen2_enable_error_correction()
98 val = ADF_CSR_RD(csr, ADF_GEN2_CERRSSMSH(i)); in adf_gen2_enable_error_correction()
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| A D | adf_gen2_hw_data.h | 31 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
34 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
37 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
87 ADF_CSR_RD(pmisc_bar_addr, AE2FUNCTION_MAP_A_OFFSET + \
93 ADF_CSR_RD(pmisc_bar_addr, AE2FUNCTION_MAP_B_OFFSET + \
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| A D | adf_gen4_hw_data.h | 28 ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
32 ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
36 ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
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| A D | icp_qat_hal.h | 128 ADF_CSR_RD((handle)->hal_cap_g_ctl_csr_addr_v, csr)
134 #define GET_AE_CSR(handle, ae, csr) ADF_CSR_RD(AE_CSR_ADDR(handle, ae, csr), 0)
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| A D | adf_vf_isr.c | 98 msg = ADF_CSR_RD(pmisc_bar_addr, hw_data->get_pf2vf_offset(0)); in adf_pf2vf_bh_handler()
190 v_int = ADF_CSR_RD(pmisc_bar_addr, ADF_VINTSOU_OFFSET); in adf_isr()
193 v_mask = ADF_CSR_RD(pmisc_bar_addr, ADF_VINTMSK_OFFSET); in adf_isr()
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| A D | adf_pf2vf_msg.c | 90 val = ADF_CSR_RD(pmisc_bar_addr, pf2vf_offset); in __adf_iov_putmsg()
107 val = ADF_CSR_RD(pmisc_bar_addr, pf2vf_offset); in __adf_iov_putmsg()
230 msg = ADF_CSR_RD(pmisc_addr, hw_data->get_pf2vf_offset(vf_nr)); in adf_vf2pf_req_hndl()
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| A D | adf_admin.c | 122 if (ADF_CSR_RD(mailbox, mb_offset) == 1) { in adf_put_admin_msg_sync()
130 ret = read_poll_timeout(ADF_CSR_RD, status, status == 0, in adf_put_admin_msg_sync()
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| A D | adf_accel_devices.h | 215 #define ADF_CSR_RD(csr_base, csr_offset) __raw_readl(csr_base + csr_offset) macro
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| A D | qat_hal.c | 453 csr_val = ADF_CSR_RD(csr_addr, 0); in qat_hal_init_esram()
457 csr_val = ADF_CSR_RD(csr_addr, 0); in qat_hal_init_esram()
463 csr_val = ADF_CSR_RD(csr_addr, 0); in qat_hal_init_esram()
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| /linux/drivers/crypto/qat/qat_dh895xcc/ |
| A D | adf_dh895xcc_hw_data.c | 125 errsou5 = ADF_CSR_RD(pmisc_bar, ADF_GEN2_ERRSOU5); in get_vf2pf_sources()
126 errmsk5 = ADF_CSR_RD(pmisc_bar, ADF_GEN2_ERRMSK5); in get_vf2pf_sources()
140 u32 val = ADF_CSR_RD(pmisc_addr, ADF_GEN2_ERRMSK5) in enable_vf2pf_interrupts()
154 u32 val = ADF_CSR_RD(pmisc_addr, ADF_GEN2_ERRMSK5) in disable_vf2pf_interrupts()
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| /linux/drivers/crypto/qat/qat_4xxx/ |
| A D | adf_4xxx_hw_data.c | 175 csr = ADF_CSR_RD(addr, ADF_4XXX_ERRMSK2); in adf_init_device()
183 ret = read_poll_timeout(ADF_CSR_RD, status, in adf_init_device()
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