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Searched refs:ADF_CSR_WR (Results 1 – 15 of 15) sorted by relevance

/linux/drivers/crypto/qat/qat_common/
A Dadf_gen2_hw_data.h40 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
47 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
49 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
54 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
57 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
60 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
64 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
66 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
90 ADF_CSR_WR(pmisc_bar_addr, AE2FUNCTION_MAP_A_OFFSET + \
96 ADF_CSR_WR(pmisc_bar_addr, AE2FUNCTION_MAP_B_OFFSET + \
[all …]
A Dadf_gen4_hw_data.h39 ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
51 ADF_CSR_WR((_csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
54 ADF_CSR_WR((_csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
60 ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
64 ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
68 ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
72 ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
76 ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
80 ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
85 ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
[all …]
A Dadf_gen2_hw_data.c39 ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK3, val); in adf_gen2_enable_vf2pf_interrupts()
50 ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK3, val); in adf_gen2_disable_vf2pf_interrupts()
87 ADF_CSR_WR(csr, ADF_GEN2_AE_CTX_ENABLES(i), val); in adf_gen2_enable_error_correction()
90 ADF_CSR_WR(csr, ADF_GEN2_AE_MISC_CONTROL(i), val); in adf_gen2_enable_error_correction()
97 ADF_CSR_WR(csr, ADF_GEN2_UERRSSMSH(i), val); in adf_gen2_enable_error_correction()
100 ADF_CSR_WR(csr, ADF_GEN2_CERRSSMSH(i), val); in adf_gen2_enable_error_correction()
299 ADF_CSR_WR(pmisc_addr, ADF_SSMWDT(i), timer_val); in adf_gen2_set_ssm_wdtimer()
301 ADF_CSR_WR(pmisc_addr, ADF_SSMWDTPKE(i), timer_val_pke); in adf_gen2_set_ssm_wdtimer()
A Dicp_qat_hal.h126 ADF_CSR_WR((handle)->hal_cap_g_ctl_csr_addr_v, csr, val)
133 ADF_CSR_WR(AE_CSR_ADDR(handle, ae, csr), 0, val)
140 ADF_CSR_WR(AE_XFER_ADDR(handle, ae, reg), 0, val)
142 ADF_CSR_WR((handle)->hal_sram_addr_v, addr, val)
A Dadf_gen4_hw_data.c135 ADF_CSR_WR(pmisc_addr, ADF_SSMWDTL_OFFSET, ssm_wdt_low); in adf_gen4_set_ssm_wdtimer()
136 ADF_CSR_WR(pmisc_addr, ADF_SSMWDTH_OFFSET, ssm_wdt_high); in adf_gen4_set_ssm_wdtimer()
138 ADF_CSR_WR(pmisc_addr, ADF_SSMWDTPKEL_OFFSET, ssm_wdt_pke_low); in adf_gen4_set_ssm_wdtimer()
139 ADF_CSR_WR(pmisc_addr, ADF_SSMWDTPKEH_OFFSET, ssm_wdt_pke_high); in adf_gen4_set_ssm_wdtimer()
A Dadf_vf_isr.c39 ADF_CSR_WR(pmisc_bar_addr, ADF_VINTMSK_OFFSET, 0x0); in adf_enable_pf2vf_interrupts()
49 ADF_CSR_WR(pmisc_bar_addr, ADF_VINTMSK_OFFSET, 0x2); in adf_disable_pf2vf_interrupts()
130 ADF_CSR_WR(pmisc_bar_addr, hw_data->get_pf2vf_offset(0), msg); in adf_pf2vf_bh_handler()
150 ADF_CSR_WR(pmisc_bar_addr, hw_data->get_pf2vf_offset(0), msg); in adf_pf2vf_bh_handler()
A Dadf_admin.c128 ADF_CSR_WR(mailbox, mb_offset, 1); in adf_put_admin_msg_sync()
262 ADF_CSR_WR(csr, adminmsg_u, upper_32_bits(reg_val)); in adf_init_admin_comms()
263 ADF_CSR_WR(csr, adminmsg_l, lower_32_bits(reg_val)); in adf_init_admin_comms()
A Dadf_hw_arbiter.c11 ADF_CSR_WR(csr_addr, (arb_offset) + \
15 ADF_CSR_WR(csr_addr, ((arb_offset) + (wt_offset)) + \
A Dadf_pf2vf_msg.c102 ADF_CSR_WR(pmisc_bar_addr, pf2vf_offset, msg | int_bit); in __adf_iov_putmsg()
124 ADF_CSR_WR(pmisc_bar_addr, pf2vf_offset, val & ~local_in_use_mask); in __adf_iov_putmsg()
239 ADF_CSR_WR(pmisc_addr, hw_data->get_pf2vf_offset(vf_nr), msg); in adf_vf2pf_req_hndl()
A Dadf_accel_devices.h211 #define ADF_CSR_WR(csr_base, csr_offset, val) \ macro
A Dqat_hal.c459 ADF_CSR_WR(csr_addr, 0, csr_val); in qat_hal_init_esram()
/linux/drivers/crypto/qat/qat_4xxx/
A Dadf_4xxx_hw_data.c93 ADF_CSR_WR(csr, ADF_4XXX_MSIX_RTTABLE_OFFSET(i), i); in set_msix_default_rttable()
148 ADF_CSR_WR(csr, ADF_4XXX_ERRMSK3, ADF_4XXX_VFLNOTIFY); in adf_enable_error_correction()
158 ADF_CSR_WR(addr, ADF_4XXX_SMIAPF_RP_X0_MASK_OFFSET, 0); in adf_enable_ints()
159 ADF_CSR_WR(addr, ADF_4XXX_SMIAPF_RP_X1_MASK_OFFSET, 0); in adf_enable_ints()
162 ADF_CSR_WR(addr, ADF_4XXX_SMIAPF_MASK_OFFSET, 0); in adf_enable_ints()
177 ADF_CSR_WR(addr, ADF_4XXX_ERRMSK2, csr); in adf_init_device()
180 ADF_CSR_WR(addr, ADF_4XXX_PM_INTERRUPT, ADF_4XXX_PM_DRV_ACTIVE); in adf_init_device()
/linux/drivers/crypto/qat/qat_dh895xcc/
A Dadf_dh895xcc_hw_data.c108 ADF_CSR_WR(addr, ADF_DH895XCC_SMIAPF0_MASK_OFFSET, in adf_enable_ints()
111 ADF_CSR_WR(addr, ADF_DH895XCC_SMIAPF1_MASK_OFFSET, in adf_enable_ints()
143 ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK5, val); in enable_vf2pf_interrupts()
157 ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK5, val); in disable_vf2pf_interrupts()
/linux/drivers/crypto/qat/qat_c3xxx/
A Dadf_c3xxx_hw_data.c88 ADF_CSR_WR(addr, ADF_C3XXX_SMIAPF0_MASK_OFFSET, in adf_enable_ints()
90 ADF_CSR_WR(addr, ADF_C3XXX_SMIAPF1_MASK_OFFSET, in adf_enable_ints()
/linux/drivers/crypto/qat/qat_c62x/
A Dadf_c62x_hw_data.c90 ADF_CSR_WR(addr, ADF_C62X_SMIAPF0_MASK_OFFSET, in adf_enable_ints()
92 ADF_CSR_WR(addr, ADF_C62X_SMIAPF1_MASK_OFFSET, in adf_enable_ints()

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