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Searched refs:BIT_0 (Results 1 – 25 of 40) sorted by relevance

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/linux/drivers/scsi/qla2xxx/
A Dqla_edif.h19 #define EDIF_SA_CTL_FLG_REPL BIT_0
44 EDB_ACTIVE = BIT_0,
78 #define SA_FLAG_INVALIDATE BIT_0
A Dqla_fw.h22 #define FO1_ENABLE_8016 BIT_0
31 #define PDO_FORCE_PLOGI BIT_0
458 #define BD_WRITE_DATA BIT_0
499 #define CF_WRITE_DATA BIT_0
541 #define TMF_WRITE_DATA BIT_0
624 #define SF_FCP_RSP_DMA BIT_0
975 #define TCF_CLEAR_ACA BIT_0
1273 #define GPEX_ENABLE (BIT_1|BIT_0)
1397 #define MDBS_ENABLED BIT_0
1762 #define VCO_DONT_UPDATE_FW BIT_0
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A Dqla_target.h226 #define ATIO_EXEC_WRITE BIT_0
421 #define EF_EN_EDIF BIT_0
484 #define CTIO7_FLAGS_DATA_OUT BIT_0 /* data from initiator */
586 #define ABTS_PARAM_ABORT_SEQ BIT_0
624 #define ABTS_CONTR_FLG_TERM_EXCHG BIT_0
843 TRC_NEW_CMD = BIT_0,
971 #define QLA24XX_MGMT_SEND_NACK BIT_0
A Dqla_def.h103 #define BIT_0 0x1 macro
490 #define SRB_LOGIN_RETRIED BIT_0
784 #define NVR_CLOCK BIT_0
1039 #define MBX_DMA_IN BIT_0
1052 #define MBX_DMA_IN BIT_0
1358 #define MBX_0 BIT_0
1593 #define GLSO_SEND_RPS BIT_0
3218 SF_SCANNING = BIT_0,
3223 FS_FC4TYPE_FCP = BIT_0,
4867 #define SWITCH_FOUND BIT_0
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A Dqla_nvme.h61 #define CF_WRITE_DATA BIT_0
A Dqla_tmpl.h60 #define CAPTURE_FLAG_PHYS_ONLY BIT_0
A Dqla_mbx.c231 if (mboxes & BIT_0) { in qla2x00_mailbox_command()
710 mcp->mb[4] = BIT_0; in qla2x00_execute_fw()
1873 mcp->mb[1] = BIT_0; in qla2x00_init_firmware()
2514 if (opt & BIT_0) in qla24xx_login_fabric()
2578 mb[1] = BIT_0; in qla24xx_login_fabric()
3640 mcp->mb[1] = BIT_0; in qla2x00_set_serdes_params()
3933 mcp->mb[2] = BIT_0; in qla2x00_set_idma_speed()
5100 opt |= BIT_0; in qla2x00_read_sfp()
5117 if (opt & BIT_0) in qla2x00_read_sfp()
5151 opt |= BIT_0; in qla2x00_write_sfp()
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A Dqla_init.c4133 (BIT_3 | BIT_2 | BIT_1 | BIT_0); in qla2x00_update_fw_options()
4144 (tx_sens & (BIT_1 | BIT_0)); in qla2x00_update_fw_options()
4151 (BIT_3 | BIT_2 | BIT_1 | BIT_0); in qla2x00_update_fw_options()
4162 (tx_sens & (BIT_1 | BIT_0)); in qla2x00_update_fw_options()
5969 0xfc, mb, BIT_1|BIT_0); in qla2x00_configure_fabric()
6468 if (mb[1] & BIT_0) { in qla2x00_fabric_login()
6477 if (mb[10] & BIT_0) in qla2x00_fabric_login()
7435 rsp->options &= ~BIT_0; in qla25xx_init_queues()
7451 req->options &= ~BIT_0; in qla25xx_init_queues()
7777 (BIT_3 | BIT_2 | BIT_1 | BIT_0); in qla24xx_nvram_config()
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A Dqla_nx.h838 #define HINT_MBX_INT_PENDING BIT_0
847 #define ISRX_NX_RISC_INT BIT_0 /* RISC interrupt. */
A Dqla_inline.h378 return (data >> 6) & BIT_0 ? FC4_PRIORITY_FCP : FC4_PRIORITY_NVME; in qla2xxx_get_fc4_priority()
A Dqla_isr.c372 if (rd_reg_word(&reg->semaphore) & BIT_0) { in qla2100_intr_handler()
575 if ((cnt == 4 || cnt == 5) && (mboxes & BIT_0)) in qla2x00_mbx_completion()
577 else if (mboxes & BIT_0) in qla2x00_mbx_completion()
1317 if (mb[2] & BIT_0) in qla2x00_async_event()
1959 if (le16_to_cpu(mbx->mb1) & BIT_0) in qla2x00_mbx_iocb_entry()
3659 if (mboxes & BIT_0) in qla24xx_mbx_completion()
3959 for (cnt = 10000; (rd_reg_dword(&reg->iobase_window) & BIT_0) == 0 && in qla2xxx_check_risc_status()
3972 for (cnt = 100; (rd_reg_dword(&reg->iobase_window) & BIT_0) == 0 && in qla2xxx_check_risc_status()
A Dqla_mid.c629 req->options |= BIT_0; in qla25xx_delete_req_que()
646 rsp->options |= BIT_0; in qla25xx_delete_rsp_que()
A Dqla_sup.c39 while ((data & BIT_0) == 0) { in qla2x00_lock_nvram_access()
128 data |= BIT_0; in qla2x00_nvram_request()
1163 if ((flags & BIT_0) == 0) in qla2xxx_flash_npiv_conf()
1236 if (!(dword & BIT_0)) in qla24xx_protect_flash()
A Dqla_iocb.c1713 #define QDSS_GOT_Q_SPACE BIT_0 in qla24xx_dif_start_scsi()
2078 #define QDSS_GOT_Q_SPACE BIT_0 in qla2xxx_dif_start_scsi_mq()
2446 opts = lio->u.logio.flags & SRB_LOGIN_COND_PLOGI ? BIT_0 : 0; in qla2x00_login_iocb()
2520 mbx->mb10 = cpu_to_le16(BIT_0); in qla2x00_adisc_iocb()
2522 mbx->mb1 = cpu_to_le16((sp->fcport->loop_id << 8) | BIT_0); in qla2x00_adisc_iocb()
/linux/drivers/scsi/
A Dqla1280.h17 #define BIT_0 0x1 macro
120 #define ISP_CFG0_1020 BIT_0 /* ISP1020 */
132 #define ISP_CFG1_SXP BIT_0 /* SXP register select */
134 #define ISP_RESET BIT_0 /* ISP soft reset */
146 #define NV_CLOCK BIT_0
160 #define CDMA_CONF_DIR BIT_0 /* DMA direction (0=fifo->host 1=host->fifo) */
177 #define DDMA_CONF_DIR BIT_0 /* DMA direction (0=fifo->host 1=host->fifo) */
203 #define BIOS_ENABLE BIT_0
567 #define RF_CONT BIT_0 /* Continuation. */
A Dqla1280.c1121 mr = BIT_3 | BIT_2 | BIT_1 | BIT_0; in qla1280_set_target_parameters()
1906 BIT_3 | BIT_2 | BIT_1 | BIT_0, in qla1280_init_rings()
1920 BIT_3 | BIT_2 | BIT_1 | BIT_0, in qla1280_init_rings()
2094 flag = (BIT_0 << target); in qla1280_config_target()
2213 BIT_7 | BIT_3 | BIT_2 | BIT_1 | BIT_0); in qla1280_nvram_config()
2248 BIT_1 | BIT_0, &mb[0]); in qla1280_nvram_config()
2371 data |= BIT_0; in qla1280_nvram_request()
2442 if (mr & BIT_0) { in qla1280_mailbox_command()
3364 if (mailbox[0] & BIT_0) { in qla1280_isr()
3427 index = mailbox[6] & BIT_0; in qla1280_isr()
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/linux/drivers/net/ethernet/qlogic/qlcnic/
A Dqlcnic_hw.h140 #define QLCNIC_GET_OWNER(val) ((val) & (BIT_0 | BIT_1))
A Dqlcnic_83xx_hw.h364 #define QLC_83XX_LINK_STATS(data) ((data) & BIT_0)
530 #define QLC_REGISTER_LB_IDC BIT_0
A Dqlcnic_hdr.h195 #define BIT_0 0x1 macro
492 #define TA_CTL_START BIT_0
A Dqlcnic_ctx.c1335 arg1 = (adapter->npars[index].phy_port & BIT_0); in qlcnic_config_switch_port()
1346 arg2 |= (BIT_0 | BIT_1); in qlcnic_config_switch_port()
1356 arg2 &= ~BIT_0; in qlcnic_config_switch_port()
1357 if (!(esw_cfg->offload_flags & BIT_0)) in qlcnic_config_switch_port()
A Dqlcnic_hw.c814 #define QLCNIC_ENABLE_IPV4_LRO BIT_0
1028 if (offload_flags & BIT_0) { in qlcnic_process_flags()
A Dqlcnic_minidump.c23 #define QLCNIC_DUMP_WCRB BIT_0
298 fw_dump->use_pex_dma = (hdr->capabilities & BIT_0) ? true : false; in qlcnic_82xx_cache_tmpl_hdr_values()
A Dqlcnic_io.c362 #define QLCNIC_ENCAP_VXLAN_PKT BIT_0
493 if (*(skb->data) & BIT_0) { in qlcnic_tx_pkt()
494 flags |= BIT_0; in qlcnic_tx_pkt()
/linux/drivers/scsi/qla4xxx/
A Dql4_fw.h54 #define HINT_MBX_INT_PENDING BIT_0
60 #define HSRX_RISC_MB_INT BIT_0 /* RISC to Host Mailbox interrupt */
64 #define ISRX_82XX_RISC_INT BIT_0 /* RISC interrupt. */
A Dql4_def.h81 #define BIT_0 0x1 macro

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