Searched refs:BIT_5 (Results 1 – 20 of 20) sorted by relevance
22 #define BIT_5 0x20 macro125 #define ISP_CFG0_1040C BIT_5 /* ISP1040C */128 #define ISP_CFG1_F64 BIT_4|BIT_5 /* 128-byte FIFO threshold */129 #define ISP_CFG1_F32 BIT_5 /* 128-byte FIFO threshold */312 #define TP_PPR BIT_5 /* PPR */
445 return BIT_5; in qla1280_data_direction()449 return BIT_5 | BIT_6; in qla1280_data_direction()1919 status = qla1280_mailbox_command(ha, BIT_7 | BIT_6 | BIT_5 | in qla1280_init_rings()2188 cfg1 = RD_REG_WORD(®->cfg_1) & ~(BIT_4 | BIT_5 | BIT_6); in qla1280_nvram_config()2260 mb[1] |= BIT_5; in qla1280_nvram_config()2265 mb[2] |= BIT_5; in qla1280_nvram_config()3910 if ((mb[2] & BIT_5) && ((mb[6] >> 8) & 0xff) >= 2) in qla1280_get_target_parameters()
85 #define OF_EXPL_CONF BIT_5 /* Explicit Confirmation Requested */179 #define NOTIFY_ACK_FLAGS_FCSP BIT_5480 #define CTIO7_FLAGS_EXPLICIT_CONFORM BIT_5749 #define NOTIFY_ACK_CLEAR_LIP_RESET BIT_5848 TRC_XMIT_STATUS = BIT_5,
108 #define BIT_5 0x20 macro495 #define SRB_LOGIN_FCSP BIT_51199 #define ADD_FO2_ENABLE_SEL_CLS2 BIT_51353 #define MBX_5 BIT_51947 #define CF_READ BIT_52015 #define PO_DISABLE_INCR_REF_TAG BIT_52347 #define NOTIFY24XX_FLAGS_FCSP BIT_52698 #define FCF_ASYNC_ACTIVE BIT_54440 #define FW_ATTR_EXT0_EDIF BIT_54869 #define DFLG_DEV_FAILED BIT_5[all …]
23 #define FO2_ENABLE_SEL_CLASS2 BIT_543 #define PDF_FCP2_CONF BIT_5908 #define LCF_SKIP_PRLI BIT_5 /* Skip PRLI after PLOGI. */909 #define LCF_IMPL_LOGO_ALL BIT_5 /* Implicit LOGO to all ports. */1188 #define CSRX_MAX_WRT_BURST_MASK (BIT_5|BIT_4)1229 #define HCCRX_RISC_RESET BIT_5 /* RISC Reset mode bit. */1510 VP_FLAGS_NAME_VALID = BIT_5,
4142 ha->fw_options[10] |= BIT_5 | in qla2x00_update_fw_options()4148 (BIT_7 | BIT_6 | BIT_5)) >> 5; in qla2x00_update_fw_options()4160 ha->fw_options[11] |= BIT_5 | in qla2x00_update_fw_options()4902 nv->firmware_options[1] = BIT_7 | BIT_5; in qla2x00_nvram_config()4903 nv->add_firmware_options[0] = BIT_5; in qla2x00_nvram_config()4910 nv->add_firmware_options[0] = BIT_5; in qla2x00_nvram_config()4915 nv->firmware_options[1] = BIT_5; in qla2x00_nvram_config()4978 (BIT_5 | BIT_4)) { in qla2x00_nvram_config()4981 nv->add_firmware_options[0] |= BIT_5; in qla2x00_nvram_config()7708 (BIT_6 | BIT_5 | BIT_4)) >> 4; in qla24xx_nvram_config()[all …]
766 options |= BIT_5; in qla25xx_create_req_que()884 options |= BIT_5; in qla25xx_create_rsp_que()
727 mcp->in_mb |= BIT_5; in qla2x00_execute_fw()2336 mcp->mb[1] |= BIT_5; in qla24xx_link_initialize()4244 vpmod->options_idx1 = BIT_3|BIT_4|BIT_5; in qla24xx_modify_vp_config()6334 if (!(subcode & (BIT_2 | BIT_5))) in qla83xx_access_control()6347 if (subcode & BIT_5) in qla83xx_access_control()6636 if ((pd->prli_svc_param_word_3[0] & BIT_5) == 0) in __qla24xx_parse_gpdb()
7017 nv->firmware_options_1 |= cpu_to_le32(BIT_5); in qlt_24xx_config_nvram_stage1()7044 tmp = ~(BIT_4|BIT_5|BIT_6); in qlt_24xx_config_nvram_stage1()7123 nv->firmware_options_1 |= cpu_to_le32(BIT_5); in qlt_81xx_config_nvram_stage1()7148 tmp = ~(BIT_4|BIT_5|BIT_6); in qlt_81xx_config_nvram_stage1()7210 vpmod->options_idx1 &= ~BIT_5; in qlt_modify_vp_config()
2149 if ((flash_data & BIT_5) && cnt > 2) in qla2x00_poll_flash()
2390 } else if (iop[0] & BIT_5) in qla24xx_logio_entry()
6060 if (sfp[0] & BIT_2 || sfp[1] & (BIT_6|BIT_5)) in qla24xx_process_purex_rdp()
1366 arg1 |= (BIT_2 | BIT_5); in qlcnic_config_switch_port()1370 arg1 |= (BIT_3 | BIT_5); in qlcnic_config_switch_port()1421 esw_cfg->host_vlan_tag = !!(arg1 & BIT_5); in qlcnic_get_eswitch_port_config()
200 #define BIT_5 0x20 macro
28 #define QLCNIC_DUMP_RD_SAVE BIT_5
923 #define QLCNIC_FW_CAPABILITY_SET_DRV_VER BIT_5
388 if (status & BIT_5) in qlcnic_sriov_get_vf_vport_info()
367 #define QLCNIC_ENCAP_DO_L4_CSUM BIT_5
86 #define BIT_5 0x20 macro
3665 SET_BITVAL(sess->discovery_logout_en, options, BIT_5); in qla4xxx_copy_to_fwddb_param()3674 SET_BITVAL(conn->tcp_nagle_disable, options, BIT_5); in qla4xxx_copy_to_fwddb_param()
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