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Searched refs:CLKID_FCLK_DIV5 (Results 1 – 11 of 11) sorted by relevance

/linux/include/dt-bindings/clock/
A Daxg-clkc.h16 #define CLKID_FCLK_DIV5 5 macro
A Dmeson8b-clkc.h15 #define CLKID_FCLK_DIV5 8 macro
A Dg12a-clkc.h16 #define CLKID_FCLK_DIV5 5 macro
A Dgxbb-clkc.h15 #define CLKID_FCLK_DIV5 7 macro
/linux/arch/arm64/boot/dts/amlogic/
A Dmeson-sm1.dtsi183 <&clkc CLKID_FCLK_DIV5>;
/linux/arch/arm/boot/dts/
A Dmeson8.dtsi711 <&clkc CLKID_FCLK_DIV5>,
A Dmeson8b.dtsi703 <&clkc CLKID_FCLK_DIV5>,
/linux/drivers/clk/meson/
A Dmeson8b.c2783 [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw,
2991 [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw,
3210 [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw,
A Dgxbb.c2701 [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw,
2913 [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw,
A Dg12a.c4254 [CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw,
4483 [CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw,
4747 [CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw,
A Daxg.c1900 [CLKID_FCLK_DIV5] = &axg_fclk_div5.hw,

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