Searched refs:CP_HQD_PQ_CONTROL (Results 1 – 9 of 9) sorted by relevance
| /linux/drivers/gpu/drm/amd/amdgpu/ |
| A D | mes_v10_1.c | 662 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, in mes_v10_1_mqd_init()
664 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, in mes_v10_1_mqd_init()
667 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); in mes_v10_1_mqd_init()
669 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); in mes_v10_1_mqd_init()
670 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); in mes_v10_1_mqd_init()
671 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); in mes_v10_1_mqd_init()
672 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); in mes_v10_1_mqd_init()
|
| A D | amdgpu_amdkfd_gfx_v10.c | 269 CP_HQD_PQ_CONTROL, QUEUE_SIZE); in kgd_hqd_load()
|
| A D | amdgpu_amdkfd_gfx_v9.c | 283 CP_HQD_PQ_CONTROL, QUEUE_SIZE); in kgd_gfx_v9_hqd_load()
|
| A D | amdgpu_amdkfd_gfx_v10_3.c | 254 CP_HQD_PQ_CONTROL, QUEUE_SIZE); in hqd_load_v10_3()
|
| A D | gfx_v9_0.c | 3558 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, in gfx_v9_0_mqd_init()
3560 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, in gfx_v9_0_mqd_init()
3563 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); in gfx_v9_0_mqd_init()
3565 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); in gfx_v9_0_mqd_init()
3566 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0); in gfx_v9_0_mqd_init()
3567 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); in gfx_v9_0_mqd_init()
3568 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); in gfx_v9_0_mqd_init()
|
| A D | gfx_v8_0.c | 4506 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, in gfx_v8_0_mqd_init()
4508 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, in gfx_v8_0_mqd_init()
4511 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); in gfx_v8_0_mqd_init()
4513 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); in gfx_v8_0_mqd_init()
4514 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0); in gfx_v8_0_mqd_init()
4515 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); in gfx_v8_0_mqd_init()
4516 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); in gfx_v8_0_mqd_init()
|
| A D | gfx_v10_0.c | 6917 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, in gfx_v10_0_compute_mqd_init()
6919 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, in gfx_v10_0_compute_mqd_init()
6922 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); in gfx_v10_0_compute_mqd_init()
6924 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); in gfx_v10_0_compute_mqd_init()
6925 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); in gfx_v10_0_compute_mqd_init()
6926 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); in gfx_v10_0_compute_mqd_init()
6927 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); in gfx_v10_0_compute_mqd_init()
|
| /linux/drivers/gpu/drm/radeon/ |
| A D | cikd.h | 1519 #define CP_HQD_PQ_CONTROL 0xC958 macro
|
| A D | cik.c | 4658 mqd->queue_state.cp_hqd_pq_control = RREG32(CP_HQD_PQ_CONTROL); in cik_cp_compute_resume()
4673 WREG32(CP_HQD_PQ_CONTROL, mqd->queue_state.cp_hqd_pq_control); in cik_cp_compute_resume()
|
Completed in 70 milliseconds