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Searched refs:DC__VOLTAGE_STATES (Results 1 – 12 of 12) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dml/
A Ddisplay_mode_vba.h420 double DCFCLKPerState[DC__VOLTAGE_STATES];
421 double DCFCLKState[DC__VOLTAGE_STATES][2];
423 double SOCCLKPerState[DC__VOLTAGE_STATES];
424 double PHYCLKPerState[DC__VOLTAGE_STATES];
426 double MaxDppclk[DC__VOLTAGE_STATES];
427 double MaxDSCCLK[DC__VOLTAGE_STATES];
429 double MaxDispclk[DC__VOLTAGE_STATES];
539 bool ModeSupport[DC__VOLTAGE_STATES][2];
541 bool DIOSupport[DC__VOLTAGE_STATES];
546 bool ROBSupport[DC__VOLTAGE_STATES][2];
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A Ddisplay_mode_structs.h73 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
A Ddc_features.h32 #define DC__VOLTAGE_STATES 9 macro
/linux/drivers/gpu/drm/amd/display/dc/dcn302/
A Ddcn302_resource.c1287 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0}; in dcn302_update_bw_bounding_box()
1288 unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0}; in dcn302_update_bw_bounding_box()
1289 unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0}; in dcn302_update_bw_bounding_box()
1290 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0}; in dcn302_update_bw_bounding_box()
1292 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {694, 875, 1000, 1200}; in dcn302_update_bw_bounding_box()
1369 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn302_update_bw_bounding_box()
1383 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { in dcn302_update_bw_bounding_box()
1388 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && in dcn302_update_bw_bounding_box()
/linux/drivers/gpu/drm/amd/display/dc/dcn303/
A Ddcn303_resource.c1217 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0}; in dcn303_update_bw_bounding_box()
1218 unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0}; in dcn303_update_bw_bounding_box()
1219 unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0}; in dcn303_update_bw_bounding_box()
1220 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0}; in dcn303_update_bw_bounding_box()
1222 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {694, 875, 1000, 1200}; in dcn303_update_bw_bounding_box()
1296 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn303_update_bw_bounding_box()
1311 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { in dcn303_update_bw_bounding_box()
1316 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && in dcn303_update_bw_bounding_box()
/linux/drivers/gpu/drm/amd/display/dc/dcn30/
A Ddcn30_resource.c2388 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0}; in dcn30_update_bw_bounding_box()
2389 unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0}; in dcn30_update_bw_bounding_box()
2390 unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0}; in dcn30_update_bw_bounding_box()
2391 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0}; in dcn30_update_bw_bounding_box()
2393 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {694, 875, 1000, 1200}; in dcn30_update_bw_bounding_box()
2472 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn30_update_bw_bounding_box()
2486 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { in dcn30_update_bw_bounding_box()
2491 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && in dcn30_update_bw_bounding_box()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn301/
A Ddcn301_fpu.c252 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; in dcn301_update_bw_bounding_box()
/linux/drivers/gpu/drm/amd/display/dc/dcn21/
A Ddcn21_resource.c1594 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; in update_bw_bounding_box()
/linux/drivers/gpu/drm/amd/display/dc/dcn31/
A Ddcn31_resource.c2059 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; in dcn31_update_bw_bounding_box()
/linux/drivers/gpu/drm/amd/display/dc/dcn20/
A Ddcn20_resource.c3541 struct _vcs_dpi_voltage_scaling_st calculated_states[DC__VOLTAGE_STATES]; in dcn20_update_bounding_box()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/
A Ddisplay_mode_vba_30.c6718 double TotalMaxPrefetchFlipDPTERowBandwidth[DC__VOLTAGE_STATES][2] = { { 0 } }; in UseMinimumDCFCLK()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/
A Ddisplay_mode_vba_31.c7312 double TotalMaxPrefetchFlipDPTERowBandwidth[DC__VOLTAGE_STATES][2];

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