| /linux/include/drm/ |
| A D | drm_dp_helper.h | 1523 #define DP_RECEIVER_CAP_SIZE 0xf macro
1531 const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
1534 const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
1737 drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_max_link_rate() argument
1743 drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_max_lane_count() argument
1784 drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_is_branch() argument
2060 u8 dpcd[DP_RECEIVER_CAP_SIZE]);
2073 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
2096 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
2100 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
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| A D | drm_dp_mst_helper.h | 656 u8 dpcd[DP_RECEIVER_CAP_SIZE];
784 bool drm_dp_read_mst_cap(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
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| /linux/drivers/gpu/drm/ |
| A D | drm_dp_helper.c | 158 const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_link_train_clock_recovery_delay() argument
192 const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_link_train_channel_eq_delay() argument
623 u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_read_extended_dpcd_caps() argument
625 u8 dpcd_ext[DP_RECEIVER_CAP_SIZE]; in drm_dp_read_extended_dpcd_caps()
677 u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_read_dpcd_caps() argument
684 if (ret != DP_RECEIVER_CAP_SIZE || dpcd[DP_DPCD_REV] == 0) in drm_dp_read_dpcd_caps()
711 const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_read_downstream_info() argument
1043 const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_downstream_mode() argument
1109 const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_downstream_debug() argument
1196 drm_dp_subconnector_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_subconnector_type() argument
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| A D | drm_dp_mst_topology.c | 3685 const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_read_mst_cap() argument
3865 DP_RECEIVER_CAP_SIZE); in drm_dp_mst_topology_mgr_resume()
3866 if (ret != DP_RECEIVER_CAP_SIZE) { in drm_dp_mst_topology_mgr_resume()
4914 ret = drm_dp_dpcd_read(mgr->aux, DP_DPCD_REV, buf, DP_RECEIVER_CAP_SIZE); in drm_dp_mst_dump_topology()
4919 seq_printf(m, "dpcd: %*ph\n", DP_RECEIVER_CAP_SIZE, buf); in drm_dp_mst_dump_topology()
5948 u8 dpcd_ext[DP_RECEIVER_CAP_SIZE]; in drm_dp_mst_dsc_aux_for_port()
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| /linux/drivers/gpu/drm/msm/dp/ |
| A D | dp_panel.c | 38 dpcd, (DP_RECEIVER_CAP_SIZE + 1)); in dp_panel_read_dpcd()
39 if (rlen < (DP_RECEIVER_CAP_SIZE + 1)) { in dp_panel_read_dpcd()
58 dpcd, (DP_RECEIVER_CAP_SIZE + 1)); in dp_panel_read_dpcd()
59 if (rlen < (DP_RECEIVER_CAP_SIZE + 1)) { in dp_panel_read_dpcd()
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| A D | dp_panel.h | 39 u8 dpcd[DP_RECEIVER_CAP_SIZE + 1];
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| /linux/drivers/gpu/drm/rockchip/ |
| A D | cdn-dp-core.h | 102 u8 dpcd[DP_RECEIVER_CAP_SIZE];
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| A D | cdn-dp-core.c | 372 DP_RECEIVER_CAP_SIZE); in cdn_dp_get_sink_capability()
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| /linux/drivers/gpu/drm/nouveau/ |
| A D | nouveau_encoder.h | 80 u8 dpcd[DP_RECEIVER_CAP_SIZE];
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| A D | atombios_dp.c | 41 #define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE
494 u8 dpcd[DP_RECEIVER_CAP_SIZE];
752 memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE); in amdgpu_atombios_dp_link_train()
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| A D | amdgpu_mode.h | 476 u8 dpcd[DP_RECEIVER_CAP_SIZE];
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| /linux/drivers/gpu/drm/radeon/ |
| A D | atombios_dp.c | 37 #define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE
545 u8 dpcd[DP_RECEIVER_CAP_SIZE];
841 memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE); in radeon_dp_link_train()
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| A D | radeon_mode.h | 489 u8 dpcd[DP_RECEIVER_CAP_SIZE];
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| /linux/drivers/gpu/drm/msm/edp/ |
| A D | edp_ctrl.c | 95 u8 dpcd[DP_RECEIVER_CAP_SIZE];
1223 DP_RECEIVER_CAP_SIZE) < DP_RECEIVER_CAP_SIZE) { in msm_edp_ctrl_panel_connected()
1225 memset(ctrl->dpcd, 0, DP_RECEIVER_CAP_SIZE); in msm_edp_ctrl_panel_connected()
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| /linux/drivers/gpu/drm/bridge/analogix/ |
| A D | analogix-anx6345.c | 64 u8 dpcd[DP_RECEIVER_CAP_SIZE];
135 &anx6345->dpcd, DP_RECEIVER_CAP_SIZE); in anx6345_dp_link_training()
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| A D | analogix-anx78xx.c | 83 u8 dpcd[DP_RECEIVER_CAP_SIZE];
647 &anx78xx->dpcd, DP_RECEIVER_CAP_SIZE); in anx78xx_dp_link_training()
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| /linux/drivers/gpu/drm/tegra/ |
| A D | dp.c | 172 u8 dpcd[DP_RECEIVER_CAP_SIZE], value; in drm_dp_link_probe()
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| /linux/drivers/gpu/drm/bridge/ |
| A D | tc358767.c | 233 u8 dpcd[DP_RECEIVER_CAP_SIZE];
674 DP_RECEIVER_CAP_SIZE); in tc_get_display_props()
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| /linux/drivers/gpu/drm/bridge/cadence/ |
| A D | cdns-mhdp8546-core.c | 1383 u8 dpcd[DP_RECEIVER_CAP_SIZE]) in cdns_mhdp_fill_sink_caps() argument
1408 u8 dpcd[DP_RECEIVER_CAP_SIZE], amp[2]; in cdns_mhdp_link_up()
1424 err = drm_dp_dpcd_read(&mhdp->aux, addr, dpcd, DP_RECEIVER_CAP_SIZE); in cdns_mhdp_link_up()
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| /linux/drivers/gpu/drm/i915/display/ |
| A D | intel_display_types.h | 1550 u8 dpcd[DP_RECEIVER_CAP_SIZE];
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| /linux/drivers/gpu/drm/xlnx/ |
| A D | zynqmp_dp.c | 317 u8 dpcd[DP_RECEIVER_CAP_SIZE];
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