| /linux/arch/mips/cavium-octeon/ |
| A D | octeon-memcpy.S | 187 EXC( LOAD t0, UNIT(0)(src), l_exc)
235 EXC( LOAD t0, UNIT(0)(src), l_exc)
262 EXC( LOAD t0, UNIT(0)(src), l_exc)
285 EXC( LOAD t0, 0(src), l_exc)
288 EXC( STORE t0, 0(dst), s_exc_p1u)
295 EXC( LOAD t0, 0(src), l_exc)
305 EXC( LOAD t0, 0(src), l_exc)
361 EXC( lb t0, N(src), l_exc); \
364 EXC( sb t0, N(dst), s_exc_p1)
372 EXC( lb t0, NBYTES-2(src), l_exc)
[all …]
|
| /linux/arch/alpha/kernel/ |
| A D | traps.c | 459 EXC(1b,3b,%1,%0) in do_entUna()
460 EXC(2b,3b,%2,%0) in do_entUna()
475 EXC(1b,3b,%1,%0) in do_entUna()
476 EXC(2b,3b,%2,%0) in do_entUna()
491 EXC(1b,3b,%1,%0) in do_entUna()
492 EXC(2b,3b,%2,%0) in do_entUna()
516 EXC(1b,5b,%2,%0) in do_entUna()
517 EXC(2b,5b,%1,%0) in do_entUna()
540 EXC(1b,5b,%2,%0) in do_entUna()
541 EXC(2b,5b,%1,%0) in do_entUna()
[all …]
|
| /linux/arch/sh/lib/ |
| A D | checksum.S | 184 #define EXC(...) \ macro
226 EXC( mov.b @r4+,r1 )
229 EXC( mov.b r1,@r5 )
260 EXC( mov.w r0,@r5 )
278 EXC( mov.l r0,@r5 )
318 EXC( mov.l @r4+,r0 )
320 EXC( mov.l r0,@r5 )
336 EXC( mov.w @r4+,r0 )
337 EXC( mov.w r0,@r5 )
346 EXC( mov.b @r4+,r0 )
[all …]
|
| /linux/arch/alpha/include/asm/ |
| A D | uaccess.h | 128 EXC(1b,2b,%0,%1) \
135 EXC(1b,2b,%0,%1) \
145 EXC(1b,2b,%0,%1) \
152 EXC(1b,2b,%0,%1) \
168 EXC(1b,3b,%0,%2) \
169 EXC(2b,3b,%0,%2) \
178 EXC(1b,2b,%0,%1) \
224 EXC(1b,2b,$31,%0) \
231 EXC(1b,2b,$31,%0) \
241 EXC(1b,2b,$31,%0) \
[all …]
|
| A D | futex.h | 23 EXC(1b,3b,$31,%1) \
24 EXC(2b,3b,$31,%1) \
84 EXC(1b,3b,$31,%0) in futex_atomic_cmpxchg_inatomic()
85 EXC(2b,3b,$31,%0) in futex_atomic_cmpxchg_inatomic()
|
| /linux/arch/mips/lib/ |
| A D | memcpy.S | 115 #define EXC(insn, type, reg, addr, handler) \ macro
149 #define LOAD(reg, addr, handler) EXC(ld, LD_INSN, reg, addr, handler)
150 #define LOADL(reg, addr, handler) EXC(ldl, LD_INSN, reg, addr, handler)
151 #define LOADR(reg, addr, handler) EXC(ldr, LD_INSN, reg, addr, handler)
154 #define STORE(reg, addr, handler) EXC(sd, ST_INSN, reg, addr, handler)
186 #define LOAD(reg, addr, handler) EXC(lw, LD_INSN, reg, addr, handler)
187 #define LOADL(reg, addr, handler) EXC(lwl, LD_INSN, reg, addr, handler)
188 #define LOADR(reg, addr, handler) EXC(lwr, LD_INSN, reg, addr, handler)
191 #define STORE(reg, addr, handler) EXC(sw, ST_INSN, reg, addr, handler)
204 #define LOADB(reg, addr, handler) EXC(lb, LD_INSN, reg, addr, handler)
[all …]
|
| A D | csum_partial.S | 346 #define EXC(insn, type, reg, addr) \ macro
372 #define LOAD(reg, addr) EXC(ld, LD_INSN, reg, addr)
374 #define LOADL(reg, addr) EXC(ldl, LD_INSN, reg, addr)
375 #define LOADR(reg, addr) EXC(ldr, LD_INSN, reg, addr)
376 #define STOREB(reg, addr) EXC(sb, ST_INSN, reg, addr)
379 #define STORE(reg, addr) EXC(sd, ST_INSN, reg, addr)
392 #define LOAD(reg, addr) EXC(lw, LD_INSN, reg, addr)
394 #define LOADL(reg, addr) EXC(lwl, LD_INSN, reg, addr)
395 #define LOADR(reg, addr) EXC(lwr, LD_INSN, reg, addr)
396 #define STOREB(reg, addr) EXC(sb, ST_INSN, reg, addr)
[all …]
|
| /linux/arch/x86/lib/ |
| A D | checksum_32.S | 263 #define EXC(y...) \ macro
288 EXC(1: movw (%esi), %bx )
290 EXC( movw %bx, (%edi) )
|
| /linux/arch/alpha/lib/ |
| A D | csum_partial_copy.c | 49 EXC(1b,2b,%0,%1) \
|
| /linux/arch/m68k/ifpsp060/src/ |
| A D | fpsp.S | 16162 # then, the SNAN bit is set in the FPSR EXC byte. If the SNAN trap #
|