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Searched refs:GATE_TOP1 (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/clk/mediatek/
A Dclk-mt8516.c527 #define GATE_TOP1(_id, _name, _parent, _shift) { \ macro
585 GATE_TOP1(CLK_TOP_I2C0, "i2c0", "ifr_i2c0_sel", 3),
586 GATE_TOP1(CLK_TOP_I2C1, "i2c1", "ifr_i2c1_sel", 4),
588 GATE_TOP1(CLK_TOP_NFI, "nfi", "nfi1x_pad_sel", 6),
591 GATE_TOP1(CLK_TOP_PWM, "pwm", "ahb_infra_sel", 9),
592 GATE_TOP1(CLK_TOP_UART0, "uart0", "uart0_sel", 10),
593 GATE_TOP1(CLK_TOP_UART1, "uart1", "uart1_sel", 11),
595 GATE_TOP1(CLK_TOP_USB, "usb", "usb_78m", 13),
599 GATE_TOP1(CLK_TOP_MSDC0, "msdc0", "msdc0_sel", 17),
600 GATE_TOP1(CLK_TOP_MSDC1, "msdc1", "msdc1_sel", 18),
[all …]
A Dclk-mt8167.c756 #define GATE_TOP1(_id, _name, _parent, _shift) { \ macro
822 GATE_TOP1(CLK_TOP_I2C0, "i2c0", "ifr_i2c0_sel", 3),
823 GATE_TOP1(CLK_TOP_I2C1, "i2c1", "ifr_i2c1_sel", 4),
825 GATE_TOP1(CLK_TOP_NFI, "nfi", "nfi1x_pad_sel", 6),
828 GATE_TOP1(CLK_TOP_PWM, "pwm", "ahb_infra_sel", 9),
829 GATE_TOP1(CLK_TOP_UART0, "uart0", "uart0_sel", 10),
830 GATE_TOP1(CLK_TOP_UART1, "uart1", "uart1_sel", 11),
832 GATE_TOP1(CLK_TOP_USB, "usb", "usb_78m", 13),
836 GATE_TOP1(CLK_TOP_MSDC0, "msdc0", "msdc0_sel", 17),
837 GATE_TOP1(CLK_TOP_MSDC1, "msdc1", "msdc1_sel", 18),
[all …]
A Dclk-mt8195-topckgen.c1186 #define GATE_TOP1(_id, _name, _parent, _shift) \ macro
1210 GATE_TOP1(CLK_TOP_SSUSB_REF, "ssusb_ref", "clk26m", 0),
1211 GATE_TOP1(CLK_TOP_SSUSB_PHY_REF, "ssusb_phy_ref", "clk26m", 1),
1212 GATE_TOP1(CLK_TOP_SSUSB_P1_REF, "ssusb_p1_ref", "clk26m", 2),
1213 GATE_TOP1(CLK_TOP_SSUSB_PHY_P1_REF, "ssusb_phy_p1_ref", "clk26m", 3),
1214 GATE_TOP1(CLK_TOP_SSUSB_P2_REF, "ssusb_p2_ref", "clk26m", 4),
1215 GATE_TOP1(CLK_TOP_SSUSB_PHY_P2_REF, "ssusb_phy_p2_ref", "clk26m", 5),
1216 GATE_TOP1(CLK_TOP_SSUSB_P3_REF, "ssusb_p3_ref", "clk26m", 6),
1217 GATE_TOP1(CLK_TOP_SSUSB_PHY_P3_REF, "ssusb_phy_p3_ref", "clk26m", 7),
A Dclk-mt6765.c494 #define GATE_TOP1(_id, _name, _parent, _shift) { \ macro
519 GATE_TOP1(CLK_TOP_ARMPLL_DIVIDER_PLL0_EN,
521 GATE_TOP1(CLK_TOP_ARMPLL_DIVIDER_PLL1_EN,
523 GATE_TOP1(CLK_TOP_ARMPLL_DIVIDER_PLL2_EN,
525 GATE_TOP1(CLK_TOP_FMEM_OCC_DRC_EN, "drc_en", "univpll2_d2", 6),
526 GATE_TOP1(CLK_TOP_USB20_48M_EN, "usb20_48m_en", "usb20_48m_div", 8),
527 GATE_TOP1(CLK_TOP_UNIVPLL_48M_EN, "univpll_48m_en", "univ_48m_div", 9),
528 GATE_TOP1(CLK_TOP_F_UFS_MP_SAP_CFG_EN, "ufs_sap", "f_f26m_ck", 12),
529 GATE_TOP1(CLK_TOP_F_BIST2FPC_EN, "bist2fpc", "f_bist2fpc_ck", 16),
A Dclk-mt7622.c79 #define GATE_TOP1(_id, _name, _parent, _shift) { \ macro
450 GATE_TOP1(CLK_TOP_A1SYS_HP_DIV_PD, "a1sys_div_pd", "a1sys_div", 0),
451 GATE_TOP1(CLK_TOP_A2SYS_HP_DIV_PD, "a2sys_div_pd", "a2sys_div", 16),
A Dclk-mt2712.c969 #define GATE_TOP1(_id, _name, _parent, _shift) { \ macro
989 GATE_TOP1(CLK_TOP_NFI2X_EN, "nfi2x_en", "nfi2x_sel", 0),
990 GATE_TOP1(CLK_TOP_NFIECC_EN, "nfiecc_en", "nfiecc_sel", 1),
991 GATE_TOP1(CLK_TOP_NFI1X_CK_EN, "nfi1x_ck_en", "nfi2x_sel", 2),

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