Home
last modified time | relevance | path

Searched refs:GC_HWIP (Results 1 – 21 of 21) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
A Dsoc15_common.h103 __WREG32_SOC15_RLC__(reg, value, AMDGPU_REGS_RLC, GC_HWIP)
110 …uint32_t r0 = adev->reg_offset[GC_HWIP][0][prefix##SCRATCH_REG0_BASE_IDX] + prefix##SCRATCH_REG0; \
111 …uint32_t r1 = adev->reg_offset[GC_HWIP][0][prefix##SCRATCH_REG1_BASE_IDX] + prefix##SCRATCH_REG1; \
112 …uint32_t spare_int = adev->reg_offset[GC_HWIP][0][prefix##RLC_SPARE_INT_BASE_IDX] + prefix##RLC_SP…
131 …5_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value, AMDGPU_REGS_RLC, GC_HWIP)
135 __RREG32_SOC15_RLC__(reg, AMDGPU_REGS_RLC, GC_HWIP)
147 …uint32_t r2 = adev->reg_offset[GC_HWIP][0][prefix##SCRATCH_REG1_BASE_IDX] + prefix##SCRATCH_REG2; \
148 …uint32_t r3 = adev->reg_offset[GC_HWIP][0][prefix##SCRATCH_REG1_BASE_IDX] + prefix##SCRATCH_REG3; \
149 …uint32_t grbm_cntl = adev->reg_offset[GC_HWIP][0][prefix##GRBM_GFX_CNTL_BASE_IDX] + prefix##GRBM_G…
150 …uint32_t grbm_idx = adev->reg_offset[GC_HWIP][0][prefix##GRBM_GFX_INDEX_BASE_IDX] + prefix##GRBM_G…
[all …]
A Damdgpu_discovery.c156 [GC_HWIP] = GC_HWID,
600 switch (adev->ip_versions[GC_HWIP][0]) { in amdgpu_discovery_set_common_ip_blocks()
626 adev->ip_versions[GC_HWIP][0]); in amdgpu_discovery_set_common_ip_blocks()
635 switch (adev->ip_versions[GC_HWIP][0]) { in amdgpu_discovery_set_gmc_ip_blocks()
661 adev->ip_versions[GC_HWIP][0]); in amdgpu_discovery_set_gmc_ip_blocks()
830 switch (adev->ip_versions[GC_HWIP][0]) { in amdgpu_discovery_set_gc_ip_blocks()
856 adev->ip_versions[GC_HWIP][0]); in amdgpu_discovery_set_gc_ip_blocks()
975 switch (adev->ip_versions[GC_HWIP][0]) { in amdgpu_discovery_set_mes_ip_blocks()
1015 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 0, 1); in amdgpu_discovery_set_ip_blocks()
1036 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 1); in amdgpu_discovery_set_ip_blocks()
[all …]
A Dgmc_v9_0.c582 (adev->ip_versions[GC_HWIP][0] < IP_VERSION(9, 4, 2))) in gmc_v9_0_process_interrupt()
699 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2)) in gmc_v9_0_use_invalidate_semaphore()
750 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 0)) { in gmc_v9_0_flush_gpu_tlb()
813 (adev->ip_versions[GC_HWIP][0] < IP_VERSION(9, 4, 2))) in gmc_v9_0_flush_gpu_tlb()
1093 if ((adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1) || in gmc_v9_0_get_vm_pte()
1094 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2)) && in gmc_v9_0_get_vm_pte()
1099 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2)) in gmc_v9_0_get_vm_pte()
1399 switch (adev->ip_versions[GC_HWIP][0]) { in gmc_v9_0_mc_init()
1515 switch (adev->ip_versions[GC_HWIP][0]) { in gmc_v9_0_sw_init()
1564 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1)) { in gmc_v9_0_sw_init()
[all …]
A Dgfx_v9_0.c961 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v9_0_init_golden_registers()
1209 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v9_0_check_fw_write_wait()
1320 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v9_0_check_if_need_gfxoff()
1674 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v9_0_init_microcode()
1975 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v9_0_rlc_init()
2155 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v9_0_gpu_early_init()
2319 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v9_0_sw_init()
2613 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v9_0_init_sq_config()
3174 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v9_0_rlc_resume()
4249 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v9_0_get_gpu_clock_counter()
[all …]
A Dgmc_v10_0.c136 (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 3, 0))) in gmc_v10_0_process_interrupt()
236 GC_HWIP : MMHUB_HWIP; in gmc_v10_0_flush_vm_hub()
271 (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 3, 0))) in gmc_v10_0_flush_vm_hub()
690 switch (adev->ip_versions[GC_HWIP][0]) { in gmc_v10_0_set_gfxhub_funcs()
860 switch (adev->ip_versions[GC_HWIP][0]) { in gmc_v10_0_sw_init()
A Dgfx_v10_0.c1470 case GC_HWIP: in gfx_v10_get_rlcg_flag()
3711 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v10_0_init_spm_golden_registers()
3734 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v10_0_init_golden_registers()
3966 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v10_0_check_fw_write_wait()
4047 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v10_0_check_gfxoff_flag()
4074 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v10_0_init_microcode()
4665 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v10_0_gpu_early_init()
4799 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v10_0_sw_init()
6318 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v10_0_cp_gfx_set_doorbell()
6567 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v10_0_kiq_setting()
[all …]
A Ddimgrey_cavefish_reg_init.c35 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in dimgrey_cavefish_reg_base_init()
A Daldebaran_reg_init.c34 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in aldebaran_reg_base_init()
A Darct_reg_init.c34 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in arct_reg_base_init()
A Dvega10_reg_init.c34 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in vega10_reg_base_init()
A Dvega20_reg_init.c34 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in vega20_reg_base_init()
A Dsoc15.c515 tmp = (entry->hwip == GC_HWIP) ? in soc15_program_register_sequence()
528 (entry->hwip == GC_HWIP) ? in soc15_program_register_sequence()
998 switch (adev->ip_versions[GC_HWIP][0]) { in soc15_common_early_init()
A Dsdma_v5_2.c72 base = adev->reg_offset[GC_HWIP][0][1]; in sdma_v5_2_get_reg_offset()
77 base = adev->reg_offset[GC_HWIP][0][0]; in sdma_v5_2_get_reg_offset()
81 base = adev->reg_offset[GC_HWIP][0][2]; in sdma_v5_2_get_reg_offset()
A Dgfxhub_v2_1.c546 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 3)) { in gfxhub_v2_1_utcl2_harvest()
A Dsdma_v5_0.c176 base = adev->reg_offset[GC_HWIP][0][1]; in sdma_v5_0_get_reg_offset()
180 base = adev->reg_offset[GC_HWIP][0][0]; in sdma_v5_0_get_reg_offset()
A Dnv.c762 switch (adev->ip_versions[GC_HWIP][0]) { in nv_common_early_init()
A Damdgpu_vcn.c139 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) in amdgpu_vcn_sw_init()
A Damdgpu.h730 GC_HWIP = 1, enumerator
/linux/drivers/gpu/drm/amd/amdkfd/
A Dkfd_device.c709 switch (adev->ip_versions[GC_HWIP][0]) { in kgd2kfd_probe()
/linux/drivers/gpu/drm/amd/pm/swsmu/
A Damdgpu_smu.c1477 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(9, 4, 2) && in smu_disable_dpms()
/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
A Damdgpu_dm.c1852 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) { in dm_dmub_sw_init()
4749 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) in fill_gfx9_tiling_info_from_device()
5190 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) in get_plane_modifiers()

Completed in 89 milliseconds