Searched refs:INTR_STATUS (Results 1 – 10 of 10) sorted by relevance
| /linux/drivers/i3c/master/mipi-i3c-hci/ |
| A D | pio.c | 252 if (!(pio_reg_read(INTR_STATUS) & STAT_RX_THLD)) in hci_pio_do_rx()
318 if (!(pio_reg_read(INTR_STATUS) & STAT_TX_THLD)) in hci_pio_do_tx()
337 if (!(pio_reg_read(INTR_STATUS) & STAT_TX_THLD)) in hci_pio_do_tx()
479 (pio_reg_read(INTR_STATUS) & STAT_RESP_READY)) { in hci_pio_process_resp()
704 if (pio_reg_read(INTR_STATUS) & STAT_RESP_READY) { in hci_pio_err()
771 if (!(pio_reg_read(INTR_STATUS) & STAT_IBI_STATUS_THLD)) in hci_pio_get_ibi_segment()
792 if (!(pio_reg_read(INTR_STATUS) & STAT_IBI_STATUS_THLD)) in hci_pio_get_ibi_segment()
906 if (!(pio_reg_read(INTR_STATUS) & STAT_IBI_STATUS_THLD)) in hci_pio_process_ibi()
916 if (!(pio_reg_read(INTR_STATUS) & STAT_IBI_STATUS_THLD)) in hci_pio_process_ibi()
988 status = pio_reg_read(INTR_STATUS); in hci_pio_irq_handler()
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| A D | core.c | 82 #define INTR_STATUS 0x20 macro
549 val = reg_read(INTR_STATUS); in i3c_hci_irq_handler()
553 reg_write(INTR_STATUS, val); in i3c_hci_irq_handler()
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| A D | dma.c | 746 status = rh_reg_read(INTR_STATUS); in hci_dma_irq_handler()
750 rh_reg_write(INTR_STATUS, status); in hci_dma_irq_handler()
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| /linux/drivers/gpu/drm/msm/disp/dpu1/ |
| A D | dpu_hwio.h | 15 #define INTR_STATUS 0x014 macro
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| A D | dpu_hw_interrupts.c | 56 MDP_SSPP_TOP0_OFF+INTR_STATUS
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| /linux/drivers/i3c/master/ |
| A D | dw-i3c-master.c | 98 #define INTR_STATUS 0x3c macro
624 writel(INTR_ALL, master->regs + INTR_STATUS); in dw_i3c_master_bus_init()
1080 status = readl(master->regs + INTR_STATUS); in dw_i3c_master_irq_handler()
1083 writel(INTR_ALL, master->regs + INTR_STATUS); in dw_i3c_master_irq_handler()
1090 writel(INTR_TRANSFER_ERR_STAT, master->regs + INTR_STATUS); in dw_i3c_master_irq_handler()
1142 writel(INTR_ALL, master->regs + INTR_STATUS); in dw_i3c_probe()
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| /linux/drivers/staging/media/tegra-vde/ |
| A D | vde.c | 33 #define INTR_STATUS 0x18 macro
147 err = readl_relaxed_poll_timeout(vde->bsev + INTR_STATUS, value, in tegra_vde_wait_bsev()
154 err = readl_relaxed_poll_timeout(vde->bsev + INTR_STATUS, value, in tegra_vde_wait_bsev()
164 err = readl_relaxed_poll_timeout(vde->bsev + INTR_STATUS, value, in tegra_vde_wait_bsev()
330 tegra_vde_writel(vde, 0x0003FC00, vde->bsev, INTR_STATUS); in tegra_vde_setup_hw_context()
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| /linux/drivers/mtd/nand/raw/ |
| A D | denali.h | 208 #define INTR_STATUS(bank) (0x410 + (bank) * 0x50) macro
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| A D | cadence-nand-controller.c | 65 #define INTR_STATUS 0x0110 macro
726 writel_relaxed(irq_status->status, cdns_ctrl->reg + INTR_STATUS); in cadence_nand_clear_interrupt()
737 irq_status->status = readl_relaxed(cdns_ctrl->reg + INTR_STATUS); in cadence_nand_read_int_status()
1181 writel_relaxed(0xFFFFFFFF, cdns_ctrl->reg + INTR_STATUS); in cadence_nand_hw_init()
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| A D | denali.c | 111 iowrite32(irq_status, denali->reg + INTR_STATUS(bank)); in denali_clear_irq()
132 irq_status = ioread32(denali->reg + INTR_STATUS(i)); in denali_isr()
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