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Searched refs:IOMEM (Results 1 – 25 of 48) sorted by relevance

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/linux/arch/arm/mach-omap1/include/mach/
A Domap1510.h58 #define OMAP1510_FPGA_REV_LOW IOMEM(OMAP1510_FPGA_BASE + 0x0)
63 #define OMAP1510_FPGA_POWER IOMEM(OMAP1510_FPGA_BASE + 0x5)
66 #define OMAP1510_FPGA_ISR_LO IOMEM(OMAP1510_FPGA_BASE + 0x6)
67 #define OMAP1510_FPGA_ISR_HI IOMEM(OMAP1510_FPGA_BASE + 0x7)
70 #define OMAP1510_FPGA_IMR_LO IOMEM(OMAP1510_FPGA_BASE + 0x8)
71 #define OMAP1510_FPGA_IMR_HI IOMEM(OMAP1510_FPGA_BASE + 0x9)
75 #define OMAP1510_FPGA_RST IOMEM(OMAP1510_FPGA_BASE + 0xb)
77 #define OMAP1510_FPGA_AUDIO IOMEM(OMAP1510_FPGA_BASE + 0xc)
78 #define OMAP1510_FPGA_DIP IOMEM(OMAP1510_FPGA_BASE + 0xe)
80 #define OMAP1510_FPGA_UART1 IOMEM(OMAP1510_FPGA_BASE + 0x14)
[all …]
A Dhardware.h76 #define OMAP1_IO_ADDRESS(pa) IOMEM((pa) - OMAP1_IO_OFFSET)
126 #define DSP_CONFIG_REG_BASE IOMEM(0xe1008000)
/linux/arch/arm/mach-spear/include/mach/
A Dspear.h22 #define VA_SPEAR_ICM1_2_BASE IOMEM(0xFD000000)
29 #define VA_SPEAR6XX_ML_CPU_BASE IOMEM(0xF0000000)
33 #define VA_SPEAR_ICM3_SMI_CTRL_BASE IOMEM(0xFC000000)
55 #define VA_PERIP_GRP2_BASE IOMEM(0xF9000000)
58 #define VA_SYSRAM0_BASE IOMEM(0xF9800000)
62 #define VA_PERIP_GRP1_BASE IOMEM(0xFD000000)
64 #define VA_UART_BASE IOMEM(0xFD000000)
67 #define VA_MISC_BASE IOMEM(0xFD700000)
70 #define VA_A9SM_AND_MPMC_BASE IOMEM(0xFC000000)
77 #define VA_A9SM_PERIP_BASE IOMEM(0xFC800000)
[all …]
/linux/arch/arm/mach-omap1/
A Dfpga.h28 #define H2P2_DBG_FPGA_FPGA_REV IOMEM(H2P2_DBG_FPGA_BASE + 0x10) /* FPGA Revision */
29 #define H2P2_DBG_FPGA_BOARD_REV IOMEM(H2P2_DBG_FPGA_BASE + 0x12) /* Board Revision */
30 #define H2P2_DBG_FPGA_GPIO IOMEM(H2P2_DBG_FPGA_BASE + 0x14) /* GPIO outputs */
31 #define H2P2_DBG_FPGA_LEDS IOMEM(H2P2_DBG_FPGA_BASE + 0x16) /* LEDs outputs */
32 #define H2P2_DBG_FPGA_MISC_INPUTS IOMEM(H2P2_DBG_FPGA_BASE + 0x18) /* Misc inputs */
33 #define H2P2_DBG_FPGA_LAN_STATUS IOMEM(H2P2_DBG_FPGA_BASE + 0x1A) /* LAN Status line */
34 #define H2P2_DBG_FPGA_LAN_RESET IOMEM(H2P2_DBG_FPGA_BASE + 0x1C) /* LAN Reset line */
/linux/arch/arm/mach-pxa/include/mach/
A Daddr-map.h24 #define PERIPH_VIRT IOMEM(0xf2000000)
32 #define SMEMC_VIRT IOMEM(0xf6000000)
39 #define DMEMC_VIRT IOMEM(0xf6100000)
51 #define NAND_VIRT IOMEM(0xf6300000)
58 #define IMEMC_VIRT IOMEM(0xfe000000)
A Dpalmtx.h72 #define PALMTX_PCMCIA_VIRT IOMEM(0xf0000000)
85 #define PALMTX_NAND_ALE_VIRT IOMEM(0xff100000)
86 #define PALMTX_NAND_CLE_VIRT IOMEM(0xff200000)
/linux/arch/arm/mach-ep93xx/
A Dts72xx.h20 #define TS72XX_MODEL_VIRT_BASE IOMEM(0xfebff000)
32 #define TS72XX_OPTIONS_VIRT_BASE IOMEM(0xfebfe000)
40 #define TS72XX_OPTIONS2_VIRT_BASE IOMEM(0xfebfd000)
47 #define TS72XX_CPLDVER_VIRT_BASE IOMEM(0xfebfc000)
/linux/arch/arm/mach-omap2/
A Diomap.h34 #define OMAP2_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L3_IO_OFFSET) /* L3 */
37 #define OMAP2_L4_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L4_IO_OFFSET) /* L4 */
40 #define OMAP4_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_IO_OFFSET) /* L3 */
43 #define AM33XX_L4_WK_IO_ADDRESS(pa) IOMEM((pa) + AM33XX_L4_WK_IO_OFFSET)
46 #define OMAP4_L3_PER_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_PER_IO_OFFSET)
49 #define OMAP2_EMU_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_EMU_IO_OFFSET)
/linux/arch/arm/mach-tegra/
A Diomap.h98 #define IO_IRAM_VIRT IOMEM(0xFE400000)
102 #define IO_CPU_VIRT IOMEM(0xFE440000)
106 #define IO_PPSB_VIRT IOMEM(0xFE200000)
110 #define IO_APB_VIRT IOMEM(0xFE000000)
/linux/arch/arm/mach-mmp/
A Daddr-map.h16 #define APB_VIRT_BASE IOMEM(0xfe000000)
20 #define AXI_VIRT_BASE IOMEM(0xfe200000)
24 #define PGU_VIRT_BASE IOMEM(0xfe400000)
/linux/arch/arm/mach-dove/
A Ddove.h28 #define DOVE_CESA_VIRT_BASE IOMEM(0xfdb00000)
41 #define DOVE_SCRATCHPAD_VIRT_BASE IOMEM(0xfdd00000)
45 #define DOVE_SB_REGS_VIRT_BASE IOMEM(0xfec00000)
49 #define DOVE_NB_REGS_VIRT_BASE IOMEM(0xfe400000)
/linux/arch/arm/mach-cns3xxx/
A Dcore.c90 gic_init(IOMEM(CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT), in cns3xxx_init_irq()
91 IOMEM(CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT)); in cns3xxx_init_irq()
96 u32 __iomem *pm_base = IOMEM(CNS3XXX_PM_BASE_VIRT); in cns3xxx_power_off()
251 cns3xxx_tmr1 = IOMEM(CNS3XXX_TIMER1_2_3_BASE_VIRT); in cns3xxx_timer_init()
378 u32 __iomem *gpioa = IOMEM(CNS3XXX_MISC_BASE_VIRT + 0x0014); in cns3xxx_init()
/linux/arch/arm/mach-ep93xx/include/mach/
A Dep93xx-regs.h23 #define EP93XX_AHB_IOMEM(x) IOMEM(EP93XX_AHB_VIRT_BASE + (x))
30 #define EP93XX_APB_IOMEM(x) IOMEM(EP93XX_APB_VIRT_BASE + (x))
/linux/arch/arm/mach-sa1100/include/mach/
A Dhardware.h36 IOMEM( (((x)&0x00ffffff) | (((x)&0x30000000)>>VIO_SHIFT)) + VIO_BASE )
40 #define __MREG(x) IOMEM(io_p2v(x))
A Duncompress.h12 #define IOMEM(x) (x) macro
/linux/arch/arm/mach-rpc/include/mach/
A Dhardware.h30 #define EASI_BASE IOMEM(0xe5000000)
34 #define IO_BASE IOMEM(0xe0000000)
/linux/arch/arm/include/asm/
A Dv7m.h5 #define V7M_SCS_ICTR IOMEM(0xe000e004)
8 #define BASEADDR_V7M_SCB IOMEM(0xe000ed00)
/linux/arch/arm/mach-pxa/
A Dzeus.h68 #define ZEUS_CPLD IOMEM(0xf0000000)
76 #define ZEUS_PC104IO IOMEM(0xf1000000)
A Dlpd270.h13 #define LPD270_CPLD_VIRT IOMEM(0xf0000000)
/linux/arch/arm/mach-mv78xx0/
A Dmv78xx0.h44 #define MV78XX0_CORE_REGS_VIRT_BASE IOMEM(0xfe400000)
52 #define MV78XX0_REGS_VIRT_BASE IOMEM(0xfec00000)
/linux/arch/arm/mach-orion5x/
A Dorion5x.h40 #define ORION5X_REGS_VIRT_BASE IOMEM(0xfec00000)
56 #define ORION5X_PCIE_WA_VIRT_BASE IOMEM(0xfd000000)
/linux/arch/arm/mach-ux500/
A Ddb8500-regs.h181 #define UX500_VIRT_ROM IOMEM(0xf0000000)
188 #define __io_address(n) IOMEM(IO_ADDRESS(n))
/linux/drivers/gpio/
A Dgpio-zevio.c64 return readl(IOMEM(c->chip.regs + section_offset + port_offset)); in zevio_gpio_port_get()
71 writel(val, IOMEM(c->chip.regs + section_offset + port_offset)); in zevio_gpio_port_set()
/linux/arch/arm/mach-ixp4xx/include/mach/
A Dixp4xx-regs.h48 #define IXP4XX_PERIPHERAL_BASE_VIRT IOMEM(0xFEC00000)
55 #define IXP4XX_PCI_CFG_BASE_VIRT IOMEM(0xFEC13000)
/linux/arch/arm/mach-davinci/include/mach/
A Dhardware.h31 #define IO_ADDRESS(pa) IOMEM(__IO_ADDRESS(pa))

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