Searched refs:Level (Results 1 – 25 of 158) sorted by relevance
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| /linux/Documentation/ABI/testing/ |
| A D | sysfs-class-backlight | 65 1 Level 1: daylight
66 2 Level 2: bright
67 3 Level 3: dark
74 1 Level 1: daylight
75 2 Level 2: bright
76 3 Level 3: office
77 4 Level 4: indoor
78 5 Level 5: dark
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| /linux/Documentation/gpu/ |
| A D | todo.rst | 42 Level: Intermediate
62 Level: Advanced
76 Level: Advanced
98 Level: Advanced
117 Level: Advanced
172 Level: Advanced
188 Level: Expert
205 Level: Starter
242 Level: Advanced
312 Level: Advanced
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| /linux/arch/arm64/boot/dts/freescale/ |
| A D | fsl-ls208xa.dtsi | 362 interrupts = <0 32 0x4>; /* Level high type */
370 interrupts = <0 32 0x4>; /* Level high type */
378 interrupts = <0 33 0x4>; /* Level high type */
386 interrupts = <0 33 0x4>; /* Level high type */
927 interrupts = <0 26 0x4>; /* Level high type */
938 interrupts = <0 28 0x4>; /* Level high type */
950 interrupts = <0 36 0x4>; /* Level high type */
961 interrupts = <0 36 0x4>; /* Level high type */
972 interrupts = <0 37 0x4>; /* Level high type */
983 interrupts = <0 37 0x4>; /* Level high type */
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| /linux/Documentation/userspace-api/media/v4l/ |
| A D | ext-ctrls-codec.rst | 820 - Level 1B
902 - Level 0
904 - Level 0b
906 - Level 1
908 - Level 2
910 - Level 3
912 - Level 3b
914 - Level 4
916 - Level 5
2206 - Level 1
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| /linux/Documentation/userspace-api/media/dvb/ |
| A D | ca_high_level.rst | 14 With the High Level CI approach any new card with almost any random
65 With this High Level CI interface, the interface can be defined with the
102 Descriptors(Program Level)=[ 09 06 06 04 05 50 ff f1]
139 | | | High Level CI driver
156 The High Level CI interface uses the EN50221 DVB standard, following a
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| /linux/Documentation/devicetree/bindings/interrupt-controller/ |
| A D | intel,ce4100-ioapic.txt | 19 1 - Level Low
20 2 - Level High
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| A D | brcm,bcm3380-l2-intc.txt | 1 Broadcom BCM3380-style Level 1 / Level 2 interrupt controller
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| A D | sifive,plic-1.0.0.yaml | 8 title: SiFive Platform-Level Interrupt Controller (PLIC)
12 Platform-Level Interrupt Controller (PLIC) high-level specification in
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| A D | brcm,l2-intc.txt | 1 Broadcom Generic Level 2 Interrupt Controller
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| A D | abilis,tb10x-ictl.txt | 1 TB10x Top Level Interrupt Controller
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| /linux/Documentation/devicetree/bindings/pinctrl/ |
| A D | renesas,rzn1-pinctrl.yaml | 68 These identifiers collapse the IO Multiplex Configuration Level 1
69 and Level 2 numbers that are detailed in the hardware reference
70 manual into a single number. The identifiers for Level 2 are simply
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| A D | qcom,tlmm-common.yaml | 7 title: Qualcomm Technologies, Inc. Top Level Mode Multiplexer (TLMM) definitions
13 This defines the common properties used to describe all Qualcomm Top Level
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| /linux/Documentation/driver-api/firmware/ |
| A D | other_interfaces.rst | 21 at Exception Level 1 (EL1), access to the features requires
22 Exception Level 3 (EL3).
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| /linux/Documentation/devicetree/bindings/arm/msm/ |
| A D | qcom,llcc.yaml | 7 title: Last Level Cache Controller
14 LLCC (Last Level Cache Controller) provides last level of cache memory in SoC,
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| /linux/arch/arc/kernel/ |
| A D | entry-compact.S | 145 ; Level 2 ISR: Can interrupt a Level 1 ISR
223 ; Level 1 ISR
342 ; Returning from Interrupts (Level 1 or 2)
346 ; Level 2 interrupt return Path - from hardware standpoint
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| A D | ctx_sw_asm.S | 16 ;################### Low Level Context Switch ##########################
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| /linux/arch/powerpc/boot/dts/ |
| A D | digsy_mtc.dts | 141 interrupts = <1 2 3>; // Level-low
148 interrupts = <1 2 3>; // Level-low
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| A D | mvme5100.dts | 61 interrupts = <1 1>; // IRQ1 Level Active Low.
72 interrupts = <1 1>; // IRQ1 Level Active Low.
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| /linux/Documentation/devicetree/bindings/sound/ |
| A D | cs35l32.txt | 8 of the AD0 pin. Level 0 is 0x40 while Level 1 is 0x41.
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| /linux/drivers/net/wireless/realtek/rtl818x/ |
| A D | Kconfig | 22 Level-One WPC-0101
70 Level 1 WNC-0301USB
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| /linux/Documentation/devicetree/bindings/riscv/ |
| A D | sifive-l2-cache.yaml | 16 The SiFive Level 2 Cache Controller is used to provide access to fast copies
17 of memory for masters in a Core Complex. The Level 2 Cache Controller also
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| /linux/Documentation/power/regulator/ |
| A D | overview.rst | 96 Regulator Level: This is defined by the regulator hardware
104 Power Domain Level: This is defined in software by kernel
112 Consumer Level: This is defined by consumer drivers
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| /linux/Documentation/networking/ |
| A D | fib_trie.rst | 16 indexed through a subset of the key. See Level Compression.
22 child array - the "child index". See Level Compression.
39 Level Compression / child arrays
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| /linux/Documentation/devicetree/bindings/nds32/ |
| A D | atl2c.txt | 5 Level-2 cache controller in general enhances overall system performance
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| /linux/Documentation/filesystems/ext4/ |
| A D | overview.rst | 3 High Level Design
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