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/linux/Documentation/devicetree/bindings/display/bridge/
A Dtoshiba,tc358762.yaml7 title: Toshiba TC358762 MIPI DSI to MIPI DPI bridge
13 The TC358762 is bridge device which converts MIPI DSI to MIPI DPI.
34 Video port for MIPI DSI input
39 Video port for MIPI DPI output (panel or connector).
A Dlontium,lt9611.yaml7 title: Lontium LT9611(UXC) 2 Port MIPI to HDMI Bridge
35 description: Regulator for 1.8V MIPI phy power.
47 Primary MIPI port-1 for MIPI input
52 Additional MIPI port-2 for MIPI input, used in combination
53 with primary MIPI port-1 to drive higher resolution displays
A Dchipone,icn6211.yaml7 title: Chipone ICN6211 MIPI-DSI to RGB Converter bridge
13 ICN6211 is MIPI-DSI to RGB Converter bridge from chipone.
15 It has a flexible configuration of MIPI DSI signal input and
31 description: A 1.8V/2.5V/3.3V supply that power the MIPI RX.
46 Video port for MIPI DSI input
51 Video port for MIPI DPI output (panel or connector).
A Dintel,keembay-dsi.yaml19 - description: MIPI registers range
27 - description: MIPI DSI clock
28 - description: MIPI DSI econfig clock
29 - description: MIPI DSI config clock
43 description: MIPI DSI input port.
A Dti,sn65dsi83.yaml13 Texas Instruments SN65DSI83 1x Single-link MIPI DSI
16 Texas Instruments SN65DSI84 1x Single-link MIPI DSI
42 description: Video port for MIPI DSI Channel-A input
62 description: Video port for MIPI DSI Channel-B input
/linux/Documentation/devicetree/bindings/media/xilinx/
A Dxlnx,csi2rxss.yaml7 title: Xilinx MIPI CSI-2 Receiver Subsystem
13 The Xilinx MIPI CSI-2 Receiver Subsystem is used to capture MIPI CSI-2
16 The subsystem consists of a MIPI D-PHY in slave mode which captures the
17 data packets. This is passed along the MIPI CSI-2 Rx IP which extracts the
20 For more details, please refer to PG232 Xilinx MIPI CSI-2 Receiver Subsystem.
21 Please note that this bindings includes only the MIPI CSI-2 Rx controller
118 connects to MIPI CSI-2 source like sensor.
196 /* MIPI CSI-2 Camera handle */
/linux/Documentation/devicetree/bindings/media/i2c/
A Dtc358743.txt1 * Toshiba TC358743 HDMI-RX to MIPI CSI2-TX Bridge
3 The Toshiba TC358743 HDMI-RX to MIPI CSI2-TX (H2C) is a bridge that converts
4 a HDMI stream to MIPI CSI-2 TX. It is programmable through I2C.
20 MIPI CSI-2 clock is continuous or non-continuous.
25 For further information on the MIPI CSI-2 endpoint node properties, see
/linux/Documentation/devicetree/bindings/phy/
A Drockchip-mipi-dphy-rx0.yaml7 title: Rockchip SoC MIPI RX0 D-PHY Device Tree Bindings
14 The Rockchip SoC has a MIPI D-PHY bus with an RX0 entry which connects to
23 - description: MIPI D-PHY ref clock
24 - description: MIPI D-PHY RX0 cfg clock
53 * MIPI D-PHY RX0 use registers in "general register files", it
/linux/drivers/phy/rockchip/
A DKconfig13 tristate "Rockchip MIPI Synopsys DPHY RX0 driver"
18 Enable this to support the Rockchip MIPI Synopsys DPHY RX0
52 tristate "Rockchip Innosilicon MIPI CSI PHY driver"
57 Enable this to support the Rockchip MIPI CSI PHY with
61 tristate "Rockchip Innosilicon MIPI/LVDS/TTL PHY driver"
66 Enable this to support the Rockchip MIPI/LVDS/TTL PHY with
/linux/Documentation/devicetree/bindings/media/
A Dsamsung-mipi-csis.txt1 Samsung S5P/Exynos SoC series MIPI CSI-2 receiver (MIPI CSIS)
11 - interrupts : should contain MIPI CSIS interrupt; the format of the
14 - vddio-supply : MIPI CSIS I/O and PLL voltage supply (e.g. 1.8V);
15 - vddcore-supply : MIPI CSIS Core voltage supply (e.g. 1.1V);
42 - data-lanes : (required) an array specifying active physical MIPI-CSI2
A Dimx.txt27 This is the device node for the MIPI CSI-2 Receiver core in the i.MX
28 SoC. This is a Synopsys Designware MIPI CSI-2 host controller core
39 - clocks : the MIPI CSI-2 receiver requires three clocks: hsi_tx
46 connecting with a MIPI CSI-2 source, and ports 1
49 MIPI CSI-2 virtual channel outputs.
A Dnxp,imx7-mipi-csi2.yaml7 title: NXP i.MX7 and i.MX8 MIPI CSI-2 receiver
14 The NXP i.MX7 and i.MX8 families contain SoCs that include a MIPI CSI-2
19 While the CSI-2 receiver is separate from the MIPI D-PHY IP core, the PHY is
40 - description: The MIPI D-PHY clock
55 description: The MIPI D-PHY digital power supply
59 - description: MIPI D-PHY slave reset
A Dvideo-interfaces.yaml90 - 1 # MIPI CSI-2 C-PHY
91 - 2 # MIPI CSI1
93 - 4 # MIPI CSI-2 D-PHY
167 lane, e.g. for 2-lane MIPI CSI-2 bus we could have "data-lanes = <1 2>;",
171 lane. This property is valid for serial busses only (e.g. MIPI CSI-2).
180 a MIPI CSI-2 bus we could have "clock-lanes = <0>;", which places the
182 only (e.g. MIPI CSI-2).
187 Allow MIPI CSI-2 non-continuous clock mode.
192 Allowed data bus frequencies. For MIPI CSI-2, for instance, this is the
/linux/Documentation/driver-api/soundwire/
A Dsummary.rst5 SoundWire is a new interface ratified in 2015 by the MIPI Alliance.
58 The MIPI SoundWire specification uses the term 'device' to refer to a Master
69 Programs all the MIPI-defined Slave registers. Represents a SoundWire
77 Driver controlling the Slave device. MIPI-specified registers are controlled
133 MIPI specification, so Bus calls the "sdw_master_port_ops" callback
141 The MIPI specification requires each Slave interface to expose a unique
154 board-file, ACPI or DT. The MIPI Software specification defines additional
198 SoundWire MIPI specification 1.1 is available at:
201 SoundWire MIPI DisCo (Discovery and Configuration) specification is
205 (publicly accessible with registration or directly accessible to MIPI
[all …]
/linux/Documentation/devicetree/bindings/soundwire/
A Dqcom,sdw.txt59 More info in MIPI Alliance SoundWire 1.0 Specifications.
68 More info in MIPI Alliance SoundWire 1.0 Specifications.
78 More info in MIPI Alliance SoundWire 1.0 Specifications.
86 More info in MIPI Alliance SoundWire 1.0 Specifications.
97 More info in MIPI Alliance SoundWire 1.0 Specifications.
107 More info in MIPI Alliance SoundWire 1.0 Specifications.
117 More info in MIPI Alliance SoundWire 1.0 Specifications.
128 More info in MIPI Alliance SoundWire 1.0 Specifications.
139 More info in MIPI Alliance SoundWire 1.0 Specifications.
151 More info in MIPI Alliance SoundWire 1.0 Specifications.
[all …]
/linux/drivers/media/platform/cadence/
A DKconfig14 tristate "Cadence MIPI-CSI2 RX Controller"
20 Support for the Cadence MIPI CSI2 Receiver controller.
26 tristate "Cadence MIPI-CSI2 TX Controller"
32 Support for the Cadence MIPI CSI2 Transceiver controller.
/linux/Documentation/devicetree/bindings/i3c/
A Dmipi-i3c-hci.yaml7 title: MIPI I3C HCI Device Tree Bindings
16 MIPI I3C Host Controller Interface
18 The MIPI I3C HCI (Host Controller Interface) specification defines
19 a common software driver interface to support compliant MIPI I3C
/linux/drivers/phy/amlogic/
A DKconfig59 Enable this to support the Meson MIPI + PCIE PHY found
64 tristate "Meson AXG MIPI + PCIE analog PHY driver"
71 Enable this to support the Meson MIPI + PCIE analog PHY
76 tristate "Meson AXG MIPI DPHY driver"
83 Enable this to support the Meson MIPI DPHY found in Meson AXG
/linux/drivers/hwtracing/stm/
A DKconfig8 Trace Protocol (STP) format as defined by MIPI STP standards.
21 exclusively until the MIPI SyS-T support was added. Use this
24 The receiving side only needs to be able to decode the MIPI
31 tristate "MIPI SyS-T STM framing protocol driver"
34 This is an implementation of MIPI SyS-T protocol to be used
40 addition to the MIPI STP, in order to extract the data.
/linux/Documentation/trace/
A Dsys-t.rst4 MIPI SyS-T over STP
7 The MIPI SyS-T protocol driver can be used with STM class devices to
11 In order to use the MIPI SyS-T protocol driver with your STM device,
33 Now, with the MIPI SyS-T protocol driver, each policy node in the
52 MIPI SyS-T message header. It is off by default as the STP already
/linux/Documentation/devicetree/bindings/display/exynos/
A Dexynos_dsim.txt1 Exynos MIPI DSI Master
19 - vddcore-supply: MIPI DSIM Core voltage supply (e.g. 1.1V)
20 - vddio-supply: MIPI DSIM I/O and PLL voltage supply (e.g. 1.8V)
23 according to DSI host bindings (see MIPI DSI bindings [1])
32 Should contain DSI peripheral nodes (see MIPI DSI bindings [1]).
/linux/Documentation/admin-guide/media/
A Dimx7.rst16 - MIPI CSI-2 Receiver
20 MIPI Camera Input ---> MIPI CSI-2 --- > |\
39 This is the MIPI CSI-2 receiver entity. It has one sink pad to receive the pixel
40 data from MIPI CSI-2 camera sensor. It has one source pad, corresponding to the
48 sensor with a parallel interface or from MIPI CSI-2 virtual channel 0. It has
55 can interface directly with Parallel and MIPI CSI-2 buses. It has 256 x 64 FIFO
76 On this platform an OV2680 MIPI CSI-2 module is connected to the internal MIPI
A Dimx.rst32 camera sensors over Parallel, BT.656/1120, and MIPI CSI-2 buses.
66 - MIPI CSI-2 Receiver for camera sensors with the MIPI CSI-2 bus
84 - Supports parallel, BT.565, and MIPI CSI-2 interfaces.
115 MIPI CSI-2 OV5640 sensor, requires the i.MX6 MIPI CSI-2 receiver. But
141 the MIPI CSI-2 stream (usually from a MIPI CSI-2 camera sensor). It has
167 MIPI CSI-2 virtual channels from imx6-mipi-csi2 entity. They have a
413 camera interface, and the OV5640 module with a MIPI CSI-2
425 The MIPI CSI-2 OV5640 module is connected to the i.MX internal MIPI CSI-2
579 i.MX6Q SabreSD with MIPI CSI-2 OV5640
583 interface OV5642 module on IPU1 CSI0, and a MIPI CSI-2 OV5640
[all …]
A Dplatform-cardlist.rst24 cdns-csi2rx Cadence MIPI-CSI2 RX Controller
25 cdns-csi2tx Cadence MIPI-CSI2 TX Controller
46 rcar-csi2 R-Car MIPI CSI-2 Receiver
55 s5p-csis S5P/EXYNOS MIPI-CSI2 receiver (MIPI-CSIS)
/linux/drivers/media/platform/exynos4-is/
A DKconfig35 tristate "S5P/EXYNOS MIPI-CSI2 receiver (MIPI-CSIS) driver"
40 This is a V4L2 driver for Samsung S5P and EXYNOS4 SoC MIPI-CSI2
41 receiver (MIPI-CSIS) devices.

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