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Searched refs:MPLL (Results 1 – 13 of 13) sorted by relevance

/linux/drivers/clk/mstar/
A DKconfig3 bool "MStar MPLL driver"
8 Support for the MPLL PLL and dividers block present on
/linux/Documentation/devicetree/bindings/clock/
A Dmstar,msc313-mpll.yaml7 title: MStar/Sigmastar MSC313 MPLL
13 The MStar/SigmaStar MSC313 and later ARMv7 chips have an MPLL block that
A Dmvebu-core-clock.txt38 3 = mpll (MPLL Clock)
/linux/drivers/clk/samsung/
A Dclk-s3c2410.c109 ALIAS(MPLL, NULL, "mpll"),
155 [mpll] = PLL(pll_s3c2410_mpll, MPLL, "mpll", "xti",
221 [mpll] = PLL(pll_s3c2440_mpll, MPLL, "mpll", "xti",
A Dclk-s3c2443.c148 ALIAS(MPLL, NULL, "mpll"),
182 PLL(pll_6552_s3c2416, MPLL, "mpll", "mpllref", LOCKCON0, MPLLCON, NULL),
234 PLL(pll_3000, MPLL, "mpll", "mpllref", LOCKCON0, MPLLCON, NULL),
A Dclk-s3c2412.c101 PLL(pll_s3c2440_mpll, MPLL, "mpll", "xti", LOCKTIME, MPLLCON, NULL),
155 ALIAS(MPLL, NULL, "mpll"),
/linux/include/dt-bindings/clock/
A Ds3c2410.h22 #define MPLL 2 macro
A Ds3c2412.h22 #define MPLL 2 macro
A Ds3c2443.h26 #define MPLL 7 macro
/linux/Documentation/devicetree/bindings/net/
A Dmdio-mux-meson-g12a.txt14 * "clkin1" : SoC 50MHz MPLL
/linux/arch/arm/boot/dts/
A Dexynos5422-odroid-core.dtsi41 /* derived from 532MHz MPLL */
133 /* derived from 532MHz MPLL */
181 /* derived from 532MHz MPLL */
/linux/drivers/clk/ingenic/
A Djz4780-cgu.c301 .pll = DEF_PLL(MPLL),
/linux/
A Dmodules.builtin.modinfo1 …=Michael Turquette <mturquette@baylibre.com>�clk_mpll.description=Amlogic MPLL driver�clk_pll.lice…

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