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Searched refs:MSR_TYPE_RW (Results 1 – 4 of 4) sorted by relevance

/linux/arch/x86/kvm/vmx/
A Dpmu_intel.c629 vmx_set_intercept_for_msr(vcpu, lbr->from + i, MSR_TYPE_RW, set); in vmx_update_intercept_for_lbr_msrs()
630 vmx_set_intercept_for_msr(vcpu, lbr->to + i, MSR_TYPE_RW, set); in vmx_update_intercept_for_lbr_msrs()
632 vmx_set_intercept_for_msr(vcpu, lbr->info + i, MSR_TYPE_RW, set); in vmx_update_intercept_for_lbr_msrs()
635 vmx_set_intercept_for_msr(vcpu, MSR_LBR_SELECT, MSR_TYPE_RW, set); in vmx_update_intercept_for_lbr_msrs()
636 vmx_set_intercept_for_msr(vcpu, MSR_LBR_TOS, MSR_TYPE_RW, set); in vmx_update_intercept_for_lbr_msrs()
A Dvmx.c2052 MSR_TYPE_RW); in vmx_set_msr()
3814 vmx_set_intercept_for_msr(vcpu, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW, in vmx_update_msr_bitmap_x2apic()
3818 vmx_enable_intercept_for_msr(vcpu, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_RW); in vmx_update_msr_bitmap_x2apic()
3830 vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_STATUS, MSR_TYPE_RW, flag); in pt_update_intercept_for_msr()
3833 vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_CR3_MATCH, MSR_TYPE_RW, flag); in pt_update_intercept_for_msr()
6873 vmx_disable_intercept_for_msr(vcpu, MSR_FS_BASE, MSR_TYPE_RW); in vmx_create_vcpu()
6874 vmx_disable_intercept_for_msr(vcpu, MSR_GS_BASE, MSR_TYPE_RW); in vmx_create_vcpu()
6875 vmx_disable_intercept_for_msr(vcpu, MSR_KERNEL_GS_BASE, MSR_TYPE_RW); in vmx_create_vcpu()
6877 vmx_disable_intercept_for_msr(vcpu, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW); in vmx_create_vcpu()
6878 vmx_disable_intercept_for_msr(vcpu, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW); in vmx_create_vcpu()
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A Dvmx.h19 #define MSR_TYPE_RW 3 macro
A Dnested.c651 MSR_FS_BASE, MSR_TYPE_RW); in nested_vmx_prepare_msr_bitmap()
654 MSR_GS_BASE, MSR_TYPE_RW); in nested_vmx_prepare_msr_bitmap()
657 MSR_KERNEL_GS_BASE, MSR_TYPE_RW); in nested_vmx_prepare_msr_bitmap()
660 MSR_IA32_SPEC_CTRL, MSR_TYPE_RW); in nested_vmx_prepare_msr_bitmap()

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