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Searched refs:MaxClock (Results 1 – 22 of 22) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
A Ddcn31_clk_mgr.c425 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in dcn31_build_watermark_ranges()
441 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in dcn31_build_watermark_ranges()
444 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF; in dcn31_build_watermark_ranges()
455 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF; in dcn31_build_watermark_ranges()
460 table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF; in dcn31_build_watermark_ranges()
A Ddcn31_smu.h53 uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz) member
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
A Dvg_clk_mgr.c413 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in vg_build_watermark_ranges()
429 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in vg_build_watermark_ranges()
432 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF; in vg_build_watermark_ranges()
443 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF; in vg_build_watermark_ranges()
448 table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF; in vg_build_watermark_ranges()
A Ddcn301_smu.h57 uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz) member
/linux/drivers/gpu/drm/amd/pm/inc/
A Dsmu10_driver_if.h52 uint16_t MaxClock; /* This is either DCFCLK or SOCCLK (in MHz) */ member
A Dsmu12_driver_if.h52 uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz) member
A Dsmu13_driver_if_yellow_carp.h51 uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz) member
A Dsmu11_driver_if_vangogh.h51 uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz) member
A Dsmu9_driver_if.h329 uint16_t MaxClock; // This is either DCEFCLK or SOCCLK (in MHz) member
A Dsmu11_driver_if.h680 uint16_t MaxClock; member
A Dsmu11_driver_if_navi10.h1022 uint16_t MaxClock; // This is either DCEFCLK or SOCCLK (in MHz) member
A Dsmu11_driver_if_sienna_cichlid.h1479 uint16_t MaxClock; // This is either DCEFCLK or SOCCLK (in MHz) member
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/
A Ddcn30_clk_mgr_smu_msg.h52 uint16_t MaxClock; // This is either DCEFCLK or SOCCLK (in MHz) member
A Ddcn30_clk_mgr.c379 …table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MaxClock = clk_mgr->base.bw_params->wm_table.nv_entr… in dcn3_notify_wm_ranges()
/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
A Dsmu_helper.c741 table->WatermarkRow[1][i].MaxClock = in smu_set_watermarks_for_clocks_ranges()
762 table->WatermarkRow[0][i].MaxClock = in smu_set_watermarks_for_clocks_ranges()
A Dsmu_helper.h37 uint16_t MaxClock; member
/linux/drivers/gpu/drm/amd/pm/swsmu/smu13/
A Dyellow_carp_ppt.c495 table->WatermarkRow[WM_DCFCLK][i].MaxClock = in yellow_carp_set_watermarks_table()
509 table->WatermarkRow[WM_SOCCLK][i].MaxClock = in yellow_carp_set_watermarks_table()
/linux/drivers/gpu/drm/amd/pm/inc/vega12/
A Dsmu9_driver_if.h573 uint16_t MaxClock; member
/linux/drivers/gpu/drm/amd/pm/swsmu/smu12/
A Drenoir_ppt.c1049 table->WatermarkRow[WM_DCFCLK][i].MaxClock = in renoir_set_watermarks_table()
1065 table->WatermarkRow[WM_SOCCLK][i].MaxClock = in renoir_set_watermarks_table()
/linux/drivers/gpu/drm/amd/pm/swsmu/smu11/
A Dvangogh_ppt.c1602 table->WatermarkRow[WM_DCFCLK][i].MaxClock = in vangogh_set_watermarks_table()
1616 table->WatermarkRow[WM_SOCCLK][i].MaxClock = in vangogh_set_watermarks_table()
A Dnavi10_ppt.c1946 table->WatermarkRow[WM_DCEFCLK][i].MaxClock = in navi10_set_watermarks_table()
1960 table->WatermarkRow[WM_SOCCLK][i].MaxClock = in navi10_set_watermarks_table()
A Dsienna_cichlid_ppt.c1578 table->WatermarkRow[WM_DCEFCLK][i].MaxClock = in sienna_cichlid_set_watermarks_table()
1592 table->WatermarkRow[WM_SOCCLK][i].MaxClock = in sienna_cichlid_set_watermarks_table()

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