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Searched refs:MinClock (Results 1 – 22 of 22) sorted by relevance

/linux/drivers/gpu/drm/amd/pm/inc/
A Dsmu10_driver_if.h51 uint16_t MinClock; /* This is either DCFCLK or SOCCLK (in MHz) */ member
A Dsmu12_driver_if.h51 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz) member
A Dsmu13_driver_if_yellow_carp.h50 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz) member
A Dsmu11_driver_if_vangogh.h50 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz) member
A Dsmu9_driver_if.h328 uint16_t MinClock; // This is either DCEFCLK or SOCCLK (in MHz) member
A Dsmu11_driver_if.h679 uint16_t MinClock; member
A Dsmu11_driver_if_navi10.h1021 uint16_t MinClock; // This is either DCEFCLK or SOCCLK (in MHz) member
A Dsmu11_driver_if_sienna_cichlid.h1478 uint16_t MinClock; // This is either DCEFCLK or SOCCLK (in MHz) member
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
A Ddcn31_clk_mgr.c424 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn31_build_watermark_ranges()
440 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn31_build_watermark_ranges()
453 table->WatermarkRow[WM_DCFCLK][0].MinClock = 0; in dcn31_build_watermark_ranges()
459 table->WatermarkRow[WM_SOCCLK][0].MinClock = 0; in dcn31_build_watermark_ranges()
A Ddcn31_smu.h52 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz) member
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/
A Ddcn30_clk_mgr_smu_msg.h51 uint16_t MinClock; // This is either DCEFCLK or SOCCLK (in MHz) member
A Ddcn30_clk_mgr.c378 …table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MinClock = clk_mgr->base.bw_params->wm_table.nv_entr… in dcn3_notify_wm_ranges()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
A Dvg_clk_mgr.c412 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in vg_build_watermark_ranges()
428 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in vg_build_watermark_ranges()
441 table->WatermarkRow[WM_DCFCLK][0].MinClock = 0; in vg_build_watermark_ranges()
447 table->WatermarkRow[WM_SOCCLK][0].MinClock = 0; in vg_build_watermark_ranges()
A Ddcn301_smu.h56 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz) member
/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
A Dsmu_helper.c737 table->WatermarkRow[1][i].MinClock = in smu_set_watermarks_for_clocks_ranges()
758 table->WatermarkRow[0][i].MinClock = in smu_set_watermarks_for_clocks_ranges()
A Dsmu_helper.h36 uint16_t MinClock; member
/linux/drivers/gpu/drm/amd/pm/swsmu/smu13/
A Dyellow_carp_ppt.c493 table->WatermarkRow[WM_DCFCLK][i].MinClock = in yellow_carp_set_watermarks_table()
507 table->WatermarkRow[WM_SOCCLK][i].MinClock = in yellow_carp_set_watermarks_table()
/linux/drivers/gpu/drm/amd/pm/inc/vega12/
A Dsmu9_driver_if.h572 uint16_t MinClock; member
/linux/drivers/gpu/drm/amd/pm/swsmu/smu12/
A Drenoir_ppt.c1047 table->WatermarkRow[WM_DCFCLK][i].MinClock = in renoir_set_watermarks_table()
1063 table->WatermarkRow[WM_SOCCLK][i].MinClock = in renoir_set_watermarks_table()
/linux/drivers/gpu/drm/amd/pm/swsmu/smu11/
A Dvangogh_ppt.c1600 table->WatermarkRow[WM_DCFCLK][i].MinClock = in vangogh_set_watermarks_table()
1614 table->WatermarkRow[WM_SOCCLK][i].MinClock = in vangogh_set_watermarks_table()
A Dnavi10_ppt.c1944 table->WatermarkRow[WM_DCEFCLK][i].MinClock = in navi10_set_watermarks_table()
1958 table->WatermarkRow[WM_SOCCLK][i].MinClock = in navi10_set_watermarks_table()
A Dsienna_cichlid_ppt.c1576 table->WatermarkRow[WM_DCEFCLK][i].MinClock = in sienna_cichlid_set_watermarks_table()
1590 table->WatermarkRow[WM_SOCCLK][i].MinClock = in sienna_cichlid_set_watermarks_table()

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