| /linux/include/dt-bindings/clock/ |
| A D | s3c2410.h | 40 #define PCLK_PWM 25 macro
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| A D | s3c2412.h | 52 #define PCLK_PWM 43 macro
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| A D | s3c2443.h | 78 #define PCLK_PWM 82 macro
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| A D | samsung,s3c64xx-clock.h | 82 #define PCLK_PWM 67 macro
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| A D | rk3036-cru.h | 71 #define PCLK_PWM 350 macro
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| A D | exynos7-clk.h | 87 #define PCLK_PWM 10 macro
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| A D | rk3128-cru.h | 112 #define PCLK_PWM 350 macro
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| A D | rk3228-cru.h | 111 #define PCLK_PWM 350 macro
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| A D | rv1108-cru.h | 120 #define PCLK_PWM 269 macro
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| A D | rk3328-cru.h | 145 #define PCLK_PWM 214 macro
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| A D | rk3288-cru.h | 142 #define PCLK_PWM 350 macro
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| /linux/drivers/clk/samsung/ |
| A D | clk-s3c2412.c | 117 GATE(PCLK_PWM, "pwm", "pclk", CLKCON, 17, 0, 0),
147 ALIAS(PCLK_PWM, NULL, "timers"),
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| A D | clk-s3c2410.c | 88 GATE(PCLK_PWM, "pwm", "pclk", CLKCON, 8, 0, 0),
100 ALIAS(PCLK_PWM, NULL, "timers"),
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| A D | clk-s3c2443.c | 133 GATE(PCLK_PWM, "pwm", "pclk", PCLKCON, 10, 0, 0),
161 ALIAS(PCLK_PWM, NULL, "timers"),
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| A D | clk-s3c64xx.c | 238 GATE_BUS(PCLK_PWM, "pclk_pwm", "pclk", PCLK_GATE, 7),
343 ALIAS(PCLK_PWM, NULL, "timers"),
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| /linux/arch/arm/boot/dts/ |
| A D | s3c2416.dtsi | 92 clocks = <&clocks PCLK_PWM>;
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| A D | rk3036.dtsi | 427 clocks = <&cru PCLK_PWM>;
437 clocks = <&cru PCLK_PWM>;
447 clocks = <&cru PCLK_PWM>;
457 clocks = <&cru PCLK_PWM>;
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| A D | rv1108.dtsi | 218 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
230 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
242 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
254 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
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| A D | s3c64xx.dtsi | 170 clocks = <&clocks PCLK_PWM>;
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| A D | rk322x.dtsi | 440 clocks = <&cru PCLK_PWM>;
450 clocks = <&cru PCLK_PWM>;
460 clocks = <&cru PCLK_PWM>;
470 clocks = <&cru PCLK_PWM>;
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| /linux/drivers/clk/rockchip/ |
| A D | clk-rk3036.c | 414 GATE(PCLK_PWM, "pclk_pwm", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 10, GFLAGS),
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| A D | clk-rk3128.c | 511 GATE(PCLK_PWM, "pclk_pwm", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 10, GFLAGS),
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| A D | clk-rk3228.c | 608 GATE(PCLK_PWM, "pclk_rk_pwm", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 7, GFLAGS),
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| A D | clk-rk3328.c | 778 GATE(PCLK_PWM, "pclk_rk_pwm", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 6, GFLAGS),
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| /linux/arch/arm64/boot/dts/rockchip/ |
| A D | rk3328.dtsi | 450 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
461 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
472 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
484 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
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