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Searched refs:PF2 (Results 1 – 21 of 21) sorted by relevance

/linux/arch/x86/include/asm/
A Dxor.h43 #define PF2(x) " prefetchnta "PF_OFFS(x)"(%[p3]) ;\n" macro
161 PF2(i) \ in xor_sse_3()
162 PF2(i + 2) \ in xor_sse_3()
216 BLK64(PF2, XO2, i) \ in xor_sse_3_pf64()
257 PF2(i) \ in xor_sse_4()
258 PF2(i + 2) \ in xor_sse_4()
319 BLK64(PF2, XO2, i) \ in xor_sse_4_pf64()
362 PF2(i) \ in xor_sse_5()
363 PF2(i + 2) \ in xor_sse_5()
431 BLK64(PF2, XO2, i) \ in xor_sse_5_pf64()
/linux/arch/arm64/boot/dts/broadcom/stingray/
A Dstingray-pcie.dtsi24 <0x102 &gic_its 0x2100 0x1>, /* PF2 */
25 <0x118 &gic_its 0x2150 0x8>, /* PF2-VF16-23 */
/linux/Documentation/devicetree/bindings/net/dsa/
A Docelot.txt41 switch port is enabled at all, the ENETC PF2 (enetc_port2) should be enabled as
/linux/arch/arm/boot/dts/
A Dsun8i-a23-a33.dtsi374 pins = "PF0", "PF1", "PF2",
436 pins = "PF2", "PF4";
A Dsun4i-a10.dtsi752 pins = "PF0", "PF1", "PF2",
831 pins = "PF2", "PF4";
A Dsun8i-a83t.dtsi788 pins = "PF0", "PF1", "PF2",
828 pins = "PF2", "PF4";
A Dsun8i-v3s.dtsi400 pins = "PF0", "PF1", "PF2", "PF3",
A Dsun7i-a20.dtsi951 pins = "PF0", "PF1", "PF2",
1069 pins = "PF2", "PF4";
A Dsun5i.dtsi505 pins = "PF0", "PF1", "PF2", "PF3",
A Dsunxi-h3-h5.dtsi439 pins = "PF0", "PF1", "PF2", "PF3",
A Dsun8i-r40.dtsi582 pins = "PF0", "PF1", "PF2",
A Dsun9i-a80.dtsi1008 pins = "PF0", "PF1" ,"PF2", "PF3",
A Dsun6i-a31.dtsi687 pins = "PF0", "PF1", "PF2",
/linux/drivers/pinctrl/renesas/
A Dpfc-shx3.c342 PINMUX_GPIO(PF2),
A Dpfc-sh7786.c458 PINMUX_GPIO(PF2),
A Dpfc-sh7785.c726 PINMUX_GPIO(PF2),
A Dpfc-sh7203.c810 PINMUX_GPIO(PF2),
A Dpfc-sh7264.c1150 PINMUX_GPIO(PF2),
A Dpfc-sh7269.c1544 PINMUX_GPIO(PF2),
/linux/arch/arm64/boot/dts/allwinner/
A Dsun50i-h6.dtsi347 pins = "PF0", "PF1", "PF2", "PF3",
A Dsun50i-a64.dtsi733 pins = "PF0", "PF1", "PF2", "PF3",

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