Searched refs:PHYCSYMCLK_CLOCK_CNTL (Results 1 – 4 of 4) sorted by relevance
| /linux/drivers/gpu/drm/amd/display/dc/dcn30/ |
| A D | dcn30_dccg.h | 36 SR(PHYCSYMCLK_CLOCK_CNTL)
47 SR(PHYCSYMCLK_CLOCK_CNTL)
57 DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_EN, mask_sh),\
58 DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_SRC_SEL, mask_sh)
66 DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_EN, mask_sh),\
67 DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_SRC_SEL, mask_sh),\
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| /linux/drivers/gpu/drm/amd/display/dc/dcn31/ |
| A D | dcn31_dccg.h | 43 SR(PHYCSYMCLK_CLOCK_CNTL),\
88 DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_EN, mask_sh),\
89 DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_SRC_SEL, mask_sh),\
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| A D | dcn31_dccg.c | 430 REG_UPDATE_2(PHYCSYMCLK_CLOCK_CNTL, in dccg31_set_physymclk()
434 REG_UPDATE_2(PHYCSYMCLK_CLOCK_CNTL, in dccg31_set_physymclk()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn20/ |
| A D | dcn20_dccg.h | 217 uint32_t PHYCSYMCLK_CLOCK_CNTL; member
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