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Searched refs:PHY_REG (Results 1 – 11 of 11) sorted by relevance

/linux/drivers/net/ethernet/intel/e1000e/
A Dich8lan.h121 #define BM_RCTL PHY_REG(BM_WUC_PAGE, 0)
122 #define BM_WUC PHY_REG(BM_WUC_PAGE, 1)
123 #define BM_WUFC PHY_REG(BM_WUC_PAGE, 2)
124 #define BM_WUS PHY_REG(BM_WUC_PAGE, 3)
140 #define HV_MUX_DATA_CTRL PHY_REG(776, 16)
166 #define CV_SMB_CTRL PHY_REG(769, 23)
184 #define HV_SMB_ADDR PHY_REG(768, 26)
200 #define HV_OEM_BITS PHY_REG(768, 25)
215 #define HV_PM_CTRL PHY_REG(770, 17)
270 #define I217_CGFREG PHY_REG(772, 29)
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A Dethtool.c1362 e1e_rphy(hw, PHY_REG(2, 21), &phy_reg); in e1000_integrated_phy_loopback()
1365 e1e_wphy(hw, PHY_REG(2, 21), phy_reg); in e1000_integrated_phy_loopback()
1370 e1e_rphy(hw, PHY_REG(769, 16), &phy_reg); in e1000_integrated_phy_loopback()
1371 e1e_wphy(hw, PHY_REG(769, 16), phy_reg | 0x000C); in e1000_integrated_phy_loopback()
1373 e1e_rphy(hw, PHY_REG(776, 16), &phy_reg); in e1000_integrated_phy_loopback()
1376 e1e_rphy(hw, PHY_REG(769, 16), &phy_reg); in e1000_integrated_phy_loopback()
1379 e1e_rphy(hw, PHY_REG(769, 20), &phy_reg); in e1000_integrated_phy_loopback()
1395 e1e_rphy(hw, PHY_REG(0, 21), &phy_reg); in e1000_integrated_phy_loopback()
1396 e1e_wphy(hw, PHY_REG(0, 21), phy_reg & ~BIT(3)); in e1000_integrated_phy_loopback()
1398 e1e_rphy(hw, PHY_REG(776, 18), &phy_reg); in e1000_integrated_phy_loopback()
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A Dich8lan.c1497 PHY_REG(776, 20), in e1000_check_for_copper_link_ich8lan()
1510 PHY_REG(776, 20), in e1000_check_for_copper_link_ich8lan()
1522 PHY_REG(776, 20), in e1000_check_for_copper_link_ich8lan()
2582 e1e_rphy(hw, PHY_REG(769, 20), &phy_reg); in e1000_lv_jumbo_workaround_ich8lan()
2646 e1e_rphy(hw, PHY_REG(769, 23), &data); in e1000_lv_jumbo_workaround_ich8lan()
2649 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data); in e1000_lv_jumbo_workaround_ich8lan()
2652 e1e_rphy(hw, PHY_REG(769, 16), &data); in e1000_lv_jumbo_workaround_ich8lan()
2657 e1e_rphy(hw, PHY_REG(776, 20), &data); in e1000_lv_jumbo_workaround_ich8lan()
2704 e1e_rphy(hw, PHY_REG(769, 23), &data); in e1000_lv_jumbo_workaround_ich8lan()
2709 e1e_rphy(hw, PHY_REG(769, 16), &data); in e1000_lv_jumbo_workaround_ich8lan()
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A Dregs.h243 #define I82579_DFT_CTRL PHY_REG(769, 20)
A Dnetdev.c3086 e1e_rphy(hw, PHY_REG(770, 26), &phy_data); in e1000_setup_rctl()
3089 e1e_wphy(hw, PHY_REG(770, 26), phy_data); in e1000_setup_rctl()
/linux/drivers/phy/rockchip/
A Dphy-rockchip-dphy-rx0.c110 #define PHY_REG(_offset, _width, _shift) \ macro
114 [GRF_DPHY_RX0_TURNREQUEST] = PHY_REG(RK3399_GRF_SOC_CON9, 4, 0),
117 [GRF_DPHY_RX0_ENABLE] = PHY_REG(RK3399_GRF_SOC_CON21, 4, 0),
125 [GRF_DPHY_TX1RX1_ENABLE] = PHY_REG(RK3399_GRF_SOC_CON23, 4, 0),
130 [GRF_DPHY_RX1_SRC_SEL] = PHY_REG(RK3399_GRF_SOC_CON24, 1, 4),
131 [GRF_DPHY_TX1RX1_BASEDIR] = PHY_REG(RK3399_GRF_SOC_CON24, 1, 5),
134 [GRF_DPHY_RX0_TESTDIN] = PHY_REG(RK3399_GRF_SOC_CON25, 8, 0),
135 [GRF_DPHY_RX0_TESTEN] = PHY_REG(RK3399_GRF_SOC_CON25, 1, 8),
136 [GRF_DPHY_RX0_TESTCLK] = PHY_REG(RK3399_GRF_SOC_CON25, 1, 9),
137 [GRF_DPHY_RX0_TESTCLR] = PHY_REG(RK3399_GRF_SOC_CON25, 1, 10),
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A Dphy-rockchip-inno-csidphy.c87 #define PHY_REG(_offset, _width, _shift) \ macro
91 [GRF_DPHY_CSIPHY_FORCERXMODE] = PHY_REG(RK1808_GRF_PD_VI_CON_OFFSET, 4, 0),
92 [GRF_DPHY_CSIPHY_CLKLANE_EN] = PHY_REG(RK1808_GRF_PD_VI_CON_OFFSET, 1, 8),
93 [GRF_DPHY_CSIPHY_DATALANE_EN] = PHY_REG(RK1808_GRF_PD_VI_CON_OFFSET, 4, 4),
97 [GRF_DPHY_CSIPHY_FORCERXMODE] = PHY_REG(RK3326_GRF_PD_VI_CON_OFFSET, 4, 0),
98 [GRF_DPHY_CSIPHY_CLKLANE_EN] = PHY_REG(RK3326_GRF_PD_VI_CON_OFFSET, 1, 8),
99 [GRF_DPHY_CSIPHY_DATALANE_EN] = PHY_REG(RK3326_GRF_PD_VI_CON_OFFSET, 4, 4),
103 [GRF_DPHY_CSIPHY_FORCERXMODE] = PHY_REG(RK3368_GRF_SOC_CON6_OFFSET, 4, 8),
A Dphy-rockchip-inno-dsidphy.c36 #define PHY_REG(first, second) (FIRST_ADDRESS(first) | \ macro
210 u32 reg = PHY_REG(first, second) << 2; in phy_update_bits()
/linux/drivers/net/dsa/
A Dlan9303_mdio.c18 #define PHY_REG(x) (((x) >> 1) & 0x1f) macro
27 mdio->bus->write(mdio->bus, PHY_ADDR(reg), PHY_REG(reg), val); in lan9303_mdio_real_write()
45 return mdio->bus->read(mdio->bus, PHY_ADDR(reg), PHY_REG(reg)); in lan9303_mdio_real_read()
/linux/drivers/net/ethernet/intel/e1000/
A De1000_hw.h2915 #define PHY_REG(page, reg) \ macro
2919 PHY_REG(769, 17) /* Port General Configuration */
2921 PHY_REG(769, 25) /* Rate Adapter Control Register */
2924 PHY_REG(770, 16) /* KMRN FIFO's control/status register */
2926 PHY_REG(770, 17) /* KMRN Power Management Control Register */
2928 PHY_REG(770, 18) /* KMRN Inband Control Register */
2930 PHY_REG(770, 19) /* KMRN Diagnostic register */
2933 PHY_REG(770, 20) /* KMRN Acknowledge Timeouts register */
2936 PHY_REG(776, 18) /* Voltage regulator control register */
2941 PHY_REG(776, 19) /* IGP3 Capability Register */
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/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192se/
A Dreg.h230 #define PHY_REG 0x02F3 macro

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