Searched refs:PLL2 (Results 1 – 11 of 11) sorted by relevance
| /linux/sound/soc/codecs/ |
| A D | ak4642.c | 114 #define PLL2 (1 << 6) macro
117 #define PLL_MASK (PLL3 | PLL2 | PLL1 | PLL0)
345 pll = PLL2; in ak4642_dai_set_sysclk()
348 pll = PLL2 | PLL0; in ak4642_dai_set_sysclk()
351 pll = PLL2 | PLL1; in ak4642_dai_set_sysclk()
354 pll = PLL2 | PLL1 | PLL0; in ak4642_dai_set_sysclk()
357 pll = PLL3 | PLL2; in ak4642_dai_set_sysclk()
360 pll = PLL3 | PLL2 | PLL0; in ak4642_dai_set_sysclk()
367 pll = PLL3 | PLL2 | PLL1; in ak4642_dai_set_sysclk()
371 pll = PLL3 | PLL2 | PLL1 | PLL0; in ak4642_dai_set_sysclk()
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| /linux/Documentation/devicetree/bindings/clock/ |
| A D | ti,cdce925.txt | 30 For all PLL1, PLL2, ... an optional child node can be used to specify spread
49 PLL2 {
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| A D | st,nomadik.txt | 30 - clock-id: must be 1 or 2 for PLL1 and PLL2 respectively
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| A D | ti,lmk04832.yaml | 40 - description: PLL2 reference clock.
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| /linux/include/dt-bindings/clock/ |
| A D | qcom,mmcc-msm8960.h | 127 #define PLL2 118 macro
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| A D | stm32mp1-clks.h | 184 #define PLL2 177 macro
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| /linux/drivers/media/dvb-frontends/ |
| A D | zl10039.c | 41 PLL2, enumerator
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| /linux/arch/arm/boot/dts/ |
| A D | ste-nomadik-stn8815.dtsi | 196 * that is parent of TIMCLK, PLL1 and PLL2
241 /* PLL2 is usually 864 MHz and divided into a few fixed rates */
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| /linux/drivers/clk/qcom/ |
| A D | mmcc-msm8960.c | 2717 [PLL2] = &pll2.clkr,
2893 [PLL2] = &pll2.clkr,
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| /linux/drivers/clk/ |
| A D | Kconfig | 185 Y4 and Y5 derive from PLL2
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| A D | clk-stm32mp1.c | 1746 PLL(PLL2, "pll2", ref12_parents, 0, RCC_PLL2CR, RCC_RCK12SELR),
2062 PLL2,
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