Searched refs:PLL_DIV (Results 1 – 5 of 5) sorted by relevance
| /linux/drivers/clk/x86/ |
| A D | clk-lgm.c | 112 #define PLL_DIV(x) ((x) + 0x04) macro
202 PLL_DIV(CGU_PLL2_CFG0), 0, PLL_DIV_WIDTH, 24, 1, 0, 0,
208 PLL_DIV(CGU_PLL0CZ_CFG0), 4, PLL_DIV_WIDTH, 25,
215 CLK_IGNORE_UNUSED, PLL_DIV(CGU_PLL0CM0_CFG0),
218 CLK_IGNORE_UNUSED, PLL_DIV(CGU_PLL0CM1_CFG0),
228 (CLK_IGNORE_UNUSED|CLK_IS_CRITICAL), PLL_DIV(CGU_PLL0B_CFG0),
406 PLL_DIV(CGU_LJPLL3_CFG0), 0, PLL_DDIV_WIDTH,
409 PLL_DIV(CGU_LJPLL3_CFG0), 6, PLL_DDIV_WIDTH,
412 PLL_DIV(CGU_LJPLL3_CFG0), 12, PLL_DDIV_WIDTH,
415 PLL_DIV(CGU_LJPLL3_CFG0), 18, PLL_DDIV_WIDTH,
[all …]
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| /linux/drivers/mfd/ |
| A D | db8500-prcmu.c | 462 PLL_DIV enumerator
470 CLK_MGT_ENTRY(SGACLK, PLL_DIV, false),
477 CLK_MGT_ENTRY(PER1CLK, PLL_DIV, true),
478 CLK_MGT_ENTRY(PER2CLK, PLL_DIV, true),
479 CLK_MGT_ENTRY(PER3CLK, PLL_DIV, true),
480 CLK_MGT_ENTRY(PER5CLK, PLL_DIV, true),
481 CLK_MGT_ENTRY(PER6CLK, PLL_DIV, true),
482 CLK_MGT_ENTRY(PER7CLK, PLL_DIV, true),
484 CLK_MGT_ENTRY(BMLCLK, PLL_DIV, true),
490 CLK_MGT_ENTRY(MCDECLK, PLL_DIV, true),
[all …]
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| /linux/drivers/clk/at91/ |
| A D | clk-pll.c | 19 #define PLL_DIV(reg) ((reg) & PLL_DIV_MASK) macro
72 div = PLL_DIV(pllr); in clk_pll_prepare()
288 calc_rate = (pll->pms.parent_rate / PLL_DIV(pllr)) * in clk_pll_restore_context()
343 pll->div = PLL_DIV(pllr); in at91_clk_register_pll()
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| /linux/drivers/clk/ |
| A D | clk-sparx5.c | 19 #define PLL_DIV GENMASK(7, 0) macro
179 val |= FIELD_PREP(PLL_DIV, conf.div); in s5_pll_set_rate()
202 conf.div = FIELD_GET(PLL_DIV, val); in s5_pll_recalc_rate()
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| /linux/arch/mips/ar7/ |
| A D | clock.c | 56 #define PLL_DIV 0x00000002 macro
194 if ((pll & (PLL_NDIV | PLL_DIV)) == (PLL_NDIV | PLL_DIV)) { in tnetd7300_get_clock()
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