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Searched refs:R9A07G044_CLK_P0_DIV2 (Results 1 – 3 of 3) sorted by relevance

/linux/drivers/clk/renesas/
A Dr9a07g044-cpg.c19 LAST_DT_CORE_CLK = R9A07G044_CLK_P0_DIV2,
116 DEF_FIXED("P0_DIV2", R9A07G044_CLK_P0_DIV2, R9A07G044_CLK_P0, 1, 2),
/linux/include/dt-bindings/clock/
A Dr9a07g044-cpg.h33 #define R9A07G044_CLK_P0_DIV2 22 macro
/linux/arch/arm64/boot/dts/renesas/
A Dr9a07g044.dtsi212 <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>,
215 assigned-clocks = <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>;

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