Home
last modified time | relevance | path

Searched refs:REG_GET_FIELD (Results 1 – 25 of 56) sorted by relevance

123

/linux/drivers/gpu/drm/amd/amdkfd/
A Dkfd_int_process_v9.c198 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, SE_ID), in event_interrupt_wq_v9()
200 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, WLT), in event_interrupt_wq_v9()
211 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, SE_ID), in event_interrupt_wq_v9()
212 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, DATA), in event_interrupt_wq_v9()
213 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, SH_ID), in event_interrupt_wq_v9()
214 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, PRIV), in event_interrupt_wq_v9()
217 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, CU_ID), in event_interrupt_wq_v9()
223 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, SE_ID), in event_interrupt_wq_v9()
224 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, DATA), in event_interrupt_wq_v9()
225 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, SH_ID), in event_interrupt_wq_v9()
[all …]
/linux/drivers/gpu/drm/amd/amdgpu/
A Dumc_v8_7.c129 (REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_GeccErrCnt, GeccErrCnt) - in umc_v8_7_query_correctable_error_count()
139 (REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_GeccErrCnt, GeccErrCnt) - in umc_v8_7_query_correctable_error_count()
146 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && in umc_v8_7_query_correctable_error_count()
147 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1) in umc_v8_7_query_correctable_error_count()
165 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 || in umc_v8_7_querry_uncorrectable_error_count()
166 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 || in umc_v8_7_querry_uncorrectable_error_count()
167 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1)) in umc_v8_7_querry_uncorrectable_error_count()
226 if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && in umc_v8_7_query_error_address()
232 lsb = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, LSB); in umc_v8_7_query_error_address()
233 err_addr = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr); in umc_v8_7_query_error_address()
[all …]
A Dumc_v6_7.c78 (REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_EccErrCnt, EccErrCnt) - in umc_v6_7_query_correctable_error_count()
88 (REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_EccErrCnt, EccErrCnt) - in umc_v6_7_query_correctable_error_count()
94 if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && in umc_v6_7_query_correctable_error_count()
95 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1) in umc_v6_7_query_correctable_error_count()
113 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 || in umc_v6_7_querry_uncorrectable_error_count()
114 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 || in umc_v6_7_querry_uncorrectable_error_count()
115 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 || in umc_v6_7_querry_uncorrectable_error_count()
116 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1)) in umc_v6_7_querry_uncorrectable_error_count()
235 if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && in umc_v6_7_query_error_address()
248 if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) in umc_v6_7_query_error_address()
[all …]
A Dumc_v6_1.c82 return REG_GET_FIELD(rsmu_umc_val, in umc_v6_1_get_umc_index_mode_state()
204 (REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_EccErrCnt, EccErrCnt) - in umc_v6_1_query_correctable_error_count()
214 (REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_EccErrCnt, EccErrCnt) - in umc_v6_1_query_correctable_error_count()
221 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && in umc_v6_1_query_correctable_error_count()
222 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1) in umc_v6_1_query_correctable_error_count()
248 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 || in umc_v6_1_querry_uncorrectable_error_count()
249 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 || in umc_v6_1_querry_uncorrectable_error_count()
250 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1)) in umc_v6_1_querry_uncorrectable_error_count()
334 if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && in umc_v6_1_query_error_address()
340 lsb = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, LSB); in umc_v6_1_query_error_address()
[all …]
A Damdgpu_mca.c36 if (REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && in amdgpu_mca_query_correctable_error_count()
37 REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1) in amdgpu_mca_query_correctable_error_count()
47 if ((REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) && in amdgpu_mca_query_uncorrectable_error_count()
48 (REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1 || in amdgpu_mca_query_uncorrectable_error_count()
49 REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 || in amdgpu_mca_query_uncorrectable_error_count()
50 REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 || in amdgpu_mca_query_uncorrectable_error_count()
51 REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 || in amdgpu_mca_query_uncorrectable_error_count()
52 REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1)) in amdgpu_mca_query_uncorrectable_error_count()
A Dgfxhub_v1_1.c54 seg_size = REG_GET_FIELD( in gfxhub_v1_1_get_xgmi_info()
58 REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL_ALDE, PF_MAX_REGION); in gfxhub_v1_1_get_xgmi_info()
61 seg_size = REG_GET_FIELD( in gfxhub_v1_1_get_xgmi_info()
65 REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL, PF_MAX_REGION); in gfxhub_v1_1_get_xgmi_info()
96 REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL_ALDE, in gfxhub_v1_1_get_xgmi_info()
100 REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL, in gfxhub_v1_1_get_xgmi_info()
A Dsmu_v11_0_i2c.c89 if (REG_GET_FIELD(en_stat, CKSVII2C_IC_ENABLE_STATUS, IC_EN)) in smu_v11_0_i2c_enable()
183 } while (REG_GET_FIELD(reg, CKSVII2C_IC_STATUS, TFE) == 0); in smu_v11_0_i2c_poll_tx_status()
191 if (REG_GET_FIELD(reg, CKSVII2C_IC_INTR_STAT, R_TX_ABRT) == 1) { in smu_v11_0_i2c_poll_tx_status()
196 if (REG_GET_FIELD(reg_c_tx_abrt_source, in smu_v11_0_i2c_poll_tx_status()
202 } else if (REG_GET_FIELD(reg_c_tx_abrt_source, in smu_v11_0_i2c_poll_tx_status()
226 if (REG_GET_FIELD(reg_c_tx_abrt_source, in smu_v11_0_i2c_poll_rx_status()
244 } while (REG_GET_FIELD(reg_ic_status, CKSVII2C_IC_STATUS, RFNE) == 0); in smu_v11_0_i2c_poll_rx_status()
291 if (!REG_GET_FIELD(reg, CKSVII2C_IC_STATUS, TFNF)) { in smu_v11_0_i2c_transmit()
414 data[bytes_received] = REG_GET_FIELD(reg, CKSVII2C_IC_DATA_CMD, DAT); in smu_v11_0_i2c_receive()
459 if ((REG_GET_FIELD(reg_ic_enable, CKSVII2C_IC_ENABLE, ENABLE) == 0) && in smu_v11_0_i2c_activity_done()
[all …]
A Dsmuio_v13_0.c86 die_id = REG_GET_FIELD(data, SMUIO_MCM_CONFIG, DIE_ID); in smuio_v13_0_get_die_id()
103 socket_id = REG_GET_FIELD(data, SMUIO_MCM_CONFIG, SOCKET_ID); in smuio_v13_0_get_socket_id()
120 data = REG_GET_FIELD(data, SMUIO_MCM_CONFIG, TOPOLOGY_ID); in smuio_v13_0_is_host_gpu_xgmi_supported()
A Dgfxhub_v2_1.c82 u32 cid = REG_GET_FIELD(status, in gfxhub_v2_1_print_l2_protection_fault_status()
92 REG_GET_FIELD(status, in gfxhub_v2_1_print_l2_protection_fault_status()
95 REG_GET_FIELD(status, in gfxhub_v2_1_print_l2_protection_fault_status()
98 REG_GET_FIELD(status, in gfxhub_v2_1_print_l2_protection_fault_status()
101 REG_GET_FIELD(status, in gfxhub_v2_1_print_l2_protection_fault_status()
104 REG_GET_FIELD(status, in gfxhub_v2_1_print_l2_protection_fault_status()
504 REG_GET_FIELD(xgmi_lfb_cntl, GCMC_VM_XGMI_LFB_CNTL, PF_MAX_REGION); in gfxhub_v2_1_get_xgmi_info()
524 REG_GET_FIELD(xgmi_lfb_cntl, GCMC_VM_XGMI_LFB_CNTL, PF_LFB_REGION); in gfxhub_v2_1_get_xgmi_info()
528 adev->gmc.xgmi.node_segment_size = REG_GET_FIELD( in gfxhub_v2_1_get_xgmi_info()
A Dgmc_v7_0.c226 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), in gmc_v7_0_mc_load_microcode()
232 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), in gmc_v7_0_mc_load_microcode()
333 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) { in gmc_v7_0_mc_init()
339 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { in gmc_v7_0_mc_init()
785 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, in gmc_v7_0_vm_decode_fault()
790 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, in gmc_v7_0_vm_decode_fault()
980 size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) * in gmc_v7_0_get_vbios_fb_size()
981 REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) * in gmc_v7_0_get_vbios_fb_size()
1300 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, in gmc_v7_0_process_interrupt()
1305 u32 protections = REG_GET_FIELD(status, in gmc_v7_0_process_interrupt()
[all …]
A Dgfx_v9_4.c711 sec_count = REG_GET_FIELD(data, VML2_MEM_ECC_CNTL, SEC_COUNT); in gfx_v9_4_query_utc_edc_status()
719 ded_count = REG_GET_FIELD(data, VML2_MEM_ECC_CNTL, DED_COUNT); in gfx_v9_4_query_utc_edc_status()
732 sec_count = REG_GET_FIELD(data, VML2_WALKER_MEM_ECC_CNTL, in gfx_v9_4_query_utc_edc_status()
741 ded_count = REG_GET_FIELD(data, VML2_WALKER_MEM_ECC_CNTL, in gfx_v9_4_query_utc_edc_status()
755 sec_count = REG_GET_FIELD(data, UTCL2_MEM_ECC_CNTL, SEC_COUNT); in gfx_v9_4_query_utc_edc_status()
763 ded_count = REG_GET_FIELD(data, UTCL2_MEM_ECC_CNTL, DED_COUNT); in gfx_v9_4_query_utc_edc_status()
776 sec_count = REG_GET_FIELD(data, ATC_L2_CACHE_2M_DSM_CNTL, in gfx_v9_4_query_utc_edc_status()
785 ded_count = REG_GET_FIELD(data, ATC_L2_CACHE_2M_DSM_CNTL, in gfx_v9_4_query_utc_edc_status()
799 sec_count = REG_GET_FIELD(data, ATC_L2_CACHE_4K_DSM_CNTL, in gfx_v9_4_query_utc_edc_status()
808 ded_count = REG_GET_FIELD(data, ATC_L2_CACHE_4K_DSM_CNTL, in gfx_v9_4_query_utc_edc_status()
[all …]
A Dgmc_v8_0.c342 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), in gmc_v8_0_tonga_mc_load_microcode()
348 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), in gmc_v8_0_tonga_mc_load_microcode()
526 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) { in gmc_v8_0_mc_init()
532 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { in gmc_v8_0_mc_init()
1019 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, in gmc_v8_0_vm_decode_fault()
1024 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, in gmc_v8_0_vm_decode_fault()
1088 size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) * in gmc_v8_0_get_vbios_fb_size()
1089 REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) * in gmc_v8_0_get_vbios_fb_size()
1475 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, in gmc_v8_0_process_interrupt()
1480 u32 protections = REG_GET_FIELD(status, in gmc_v8_0_process_interrupt()
[all …]
A Ddf_v3_6.c228 adev->df.hash_status.hash_64k = REG_GET_FIELD(tmp, in df_v3_6_query_hashes()
231 adev->df.hash_status.hash_2m = REG_GET_FIELD(tmp, in df_v3_6_query_hashes()
234 adev->df.hash_status.hash_1g = REG_GET_FIELD(tmp, in df_v3_6_query_hashes()
650 v0 = REG_GET_FIELD(hw_assert_msklo, in df_v3_6_query_ras_poison_mode()
652 v1 = REG_GET_FIELD(hw_assert_msklo, in df_v3_6_query_ras_poison_mode()
654 v28 = REG_GET_FIELD(hw_assert_mskhi, in df_v3_6_query_ras_poison_mode()
656 v31 = REG_GET_FIELD(hw_assert_mskhi, in df_v3_6_query_ras_poison_mode()
A Dgfxhub_v2_0.c79 u32 cid = REG_GET_FIELD(status, in gfxhub_v2_0_print_l2_protection_fault_status()
89 REG_GET_FIELD(status, in gfxhub_v2_0_print_l2_protection_fault_status()
92 REG_GET_FIELD(status, in gfxhub_v2_0_print_l2_protection_fault_status()
95 REG_GET_FIELD(status, in gfxhub_v2_0_print_l2_protection_fault_status()
98 REG_GET_FIELD(status, in gfxhub_v2_0_print_l2_protection_fault_status()
101 REG_GET_FIELD(status, in gfxhub_v2_0_print_l2_protection_fault_status()
A Diceland_ih.c197 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in iceland_ih_get_wptr()
203 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in iceland_ih_get_wptr()
349 if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) in iceland_ih_is_idle()
364 if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) in iceland_ih_wait_for_idle()
A Dcz_ih.c197 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in cz_ih_get_wptr()
203 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in cz_ih_get_wptr()
350 if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) in cz_ih_is_idle()
365 if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) in cz_ih_wait_for_idle()
A Dgmc_v6_0.c71 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) { in gmc_v6_0_mc_stop()
618 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); in gmc_v6_0_vm_decode_fault()
619 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, in gmc_v6_0_vm_decode_fault()
624 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, in gmc_v6_0_vm_decode_fault()
629 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, in gmc_v6_0_vm_decode_fault()
806 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { in gmc_v6_0_get_vbios_fb_size()
810 size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) * in gmc_v6_0_get_vbios_fb_size()
811 REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) * in gmc_v6_0_get_vbios_fb_size()
A Dgmc_v9_0.c586 cid = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, CID); in gmc_v9_0_process_interrupt()
587 rw = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, RW); in gmc_v9_0_process_interrupt()
632 REG_GET_FIELD(status, in gmc_v9_0_process_interrupt()
635 REG_GET_FIELD(status, in gmc_v9_0_process_interrupt()
638 REG_GET_FIELD(status, in gmc_v9_0_process_interrupt()
641 REG_GET_FIELD(status, in gmc_v9_0_process_interrupt()
1108 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { in gmc_v9_0_get_vbios_fb_size()
1118 size = (REG_GET_FIELD(viewport, in gmc_v9_0_get_vbios_fb_size()
1120 REG_GET_FIELD(viewport, in gmc_v9_0_get_vbios_fb_size()
1126 size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) * in gmc_v9_0_get_vbios_fb_size()
[all …]
A Dtonga_ih.c199 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in tonga_ih_get_wptr()
205 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in tonga_ih_get_wptr()
361 if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) in tonga_ih_is_idle()
376 if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) in tonga_ih_wait_for_idle()
A Dmmhub_v2_0.c148 cid = REG_GET_FIELD(status, in mmhub_v2_0_print_l2_protection_fault_status()
150 rw = REG_GET_FIELD(status, in mmhub_v2_0_print_l2_protection_fault_status()
175 REG_GET_FIELD(status, in mmhub_v2_0_print_l2_protection_fault_status()
178 REG_GET_FIELD(status, in mmhub_v2_0_print_l2_protection_fault_status()
181 REG_GET_FIELD(status, in mmhub_v2_0_print_l2_protection_fault_status()
184 REG_GET_FIELD(status, in mmhub_v2_0_print_l2_protection_fault_status()
A Dmmhub_v2_3.c85 cid = REG_GET_FIELD(status, in mmhub_v2_3_print_l2_protection_fault_status()
87 rw = REG_GET_FIELD(status, in mmhub_v2_3_print_l2_protection_fault_status()
105 REG_GET_FIELD(status, in mmhub_v2_3_print_l2_protection_fault_status()
108 REG_GET_FIELD(status, in mmhub_v2_3_print_l2_protection_fault_status()
111 REG_GET_FIELD(status, in mmhub_v2_3_print_l2_protection_fault_status()
114 REG_GET_FIELD(status, in mmhub_v2_3_print_l2_protection_fault_status()
A Dnbio_v7_4.c382 if (REG_GET_FIELD(bif_doorbell_intr_cntl, in nbio_v7_4_handle_ras_controller_intr_no_bifring()
438 if (REG_GET_FIELD(bif_doorbell_intr_cntl, in nbio_v7_4_handle_ras_err_event_athub_intr_no_bifring()
605 corr = REG_GET_FIELD(global_sts, RAS_GLOBAL_STATUS_LO, ParityErrCorr); in nbio_v7_4_query_ras_error_count()
606 fatal = REG_GET_FIELD(global_sts, RAS_GLOBAL_STATUS_LO, ParityErrFatal); in nbio_v7_4_query_ras_error_count()
607 non_fatal = REG_GET_FIELD(global_sts, RAS_GLOBAL_STATUS_LO, in nbio_v7_4_query_ras_error_count()
638 if (REG_GET_FIELD(central_sts, BIFL_RAS_CENTRAL_STATUS, in nbio_v7_4_query_ras_error_count()
A Damdgpu_amdkfd_gfx_v7.c455 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, PROCESSING_IQ)) { in kgd_hqd_destroy()
459 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, ACTIVE)) { in kgd_hqd_destroy()
460 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, RETRY_TYPE) in kgd_hqd_destroy()
467 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, WAIT_TIME) in kgd_hqd_destroy()
685 return REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); in read_vmid_from_vmfault_reg()
A Dgfx_v8_0.c1839 adev->gfx.config.num_banks = REG_GET_FIELD(mc_arb_ramcfg, in gfx_v8_0_gpu_early_init()
1841 adev->gfx.config.num_ranks = REG_GET_FIELD(mc_arb_ramcfg, in gfx_v8_0_gpu_early_init()
1873 tmp = REG_GET_FIELD(mc_arb_ramcfg, MC_ARB_RAMCFG, NOOFCOLS); in gfx_v8_0_gpu_early_init()
4995 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) in gfx_v8_0_check_soft_reset()
4999 if (REG_GET_FIELD(tmp, GRBM_STATUS2, CPF_BUSY) || in gfx_v8_0_check_soft_reset()
5000 REG_GET_FIELD(tmp, GRBM_STATUS2, CPC_BUSY) || in gfx_v8_0_check_soft_reset()
5001 REG_GET_FIELD(tmp, GRBM_STATUS2, CPG_BUSY)) { in gfx_v8_0_check_soft_reset()
5014 if (REG_GET_FIELD(tmp, SRBM_STATUS, GRBM_RQ_PENDING)) in gfx_v8_0_check_soft_reset()
5017 if (REG_GET_FIELD(tmp, SRBM_STATUS, SEM_BUSY)) in gfx_v8_0_check_soft_reset()
6750 REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, WLT), in gfx_v8_0_parse_sq_irq()
[all …]
/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
A Dvega20_thermal.c124 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1), in vega20_fan_ctrl_get_fan_speed_pwm()
126 duty = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_THERMAL_STATUS), in vega20_fan_ctrl_get_fan_speed_pwm()
152 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1), in vega20_fan_ctrl_set_fan_speed_pwm()

Completed in 57 milliseconds

123