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Searched refs:REG_SET (Results 1 – 25 of 75) sorted by relevance

123

/linux/drivers/gpu/drm/amd/display/dc/dcn30/
A Ddcn30_hubp.c61 REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0, in hubp3_set_vm_system_aperture_settings()
64 REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0, in hubp3_set_vm_system_aperture_settings()
129 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, in hubp3_program_surface_flip_and_addr()
133 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, in hubp3_program_surface_flip_and_addr()
170 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0, in hubp3_program_surface_flip_and_addr()
178 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, in hubp3_program_surface_flip_and_addr()
247 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS, 0, in hubp3_program_surface_flip_and_addr()
255 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0, in hubp3_program_surface_flip_and_addr()
263 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, in hubp3_program_surface_flip_and_addr()
301 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0, in hubp3_program_surface_flip_and_addr()
[all …]
A Ddcn30_dpp_cm.c100 REG_SET(CM_GAMCOR_LUT_DATA, 0, CM_GAMCOR_LUT_DATA, rgb[i].red_reg); in dpp3_program_gammcor_lut()
108 REG_SET(CM_GAMCOR_LUT_DATA, 0, CM_GAMCOR_LUT_DATA, rgb[i].red_reg); in dpp3_program_gammcor_lut()
112 REG_SET(CM_GAMCOR_LUT_INDEX, 0, CM_GAMCOR_LUT_INDEX, 0); in dpp3_program_gammcor_lut()
121 REG_SET(CM_GAMCOR_LUT_INDEX, 0, CM_GAMCOR_LUT_INDEX, 0); in dpp3_program_gammcor_lut()
147 REG_SET(CM_MEM_PWR_CTRL, 0, in dpp3_power_on_gamcor_lut()
168 REG_SET(CM_BIAS_CR_R, 0, CM_BIAS_CR_R, bias_params->cm_bias_cr_r); in dpp3_program_cm_bias()
217 REG_SET(CM_GAMCOR_LUT_INDEX, 0, CM_GAMCOR_LUT_INDEX, 0); in dpp3_configure_gamcor_lut()
232 REG_SET(CM_GAMCOR_CONTROL, 0, CM_GAMCOR_MODE, 0); in dpp3_program_gamcor_lut()
238 REG_SET(CM_GAMCOR_CONTROL, 0, CM_GAMCOR_MODE, 2); in dpp3_program_gamcor_lut()
329 REG_SET(CM_GAMUT_REMAP_CONTROL, 0, in program_gamut_remap()
[all …]
A Ddcn30_dwb_cm.c183 REG_SET(DWB_OGAM_LUT_INDEX, 0, DWB_OGAM_LUT_INDEX, 0); in dwb3_configure_ogam_lut()
198 REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, rgb[i].red_reg); in dwb3_program_ogam_pwl()
208 REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, rgb[i].red_reg); in dwb3_program_ogam_pwl()
212 REG_SET(DWB_OGAM_LUT_INDEX, 0, DWB_OGAM_LUT_INDEX, 0); in dwb3_program_ogam_pwl()
218 REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, rgb[i].green_reg); in dwb3_program_ogam_pwl()
222 REG_SET(DWB_OGAM_LUT_INDEX, 0, DWB_OGAM_LUT_INDEX, 0); in dwb3_program_ogam_pwl()
228 REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, rgb[i].blue_reg); in dwb3_program_ogam_pwl()
242 REG_SET(DWB_OGAM_CONTROL, 0, DWB_OGAM_MODE, 0); in dwb3_program_ogam_lut()
246 REG_SET(DWB_OGAM_CONTROL, 0, DWB_OGAM_MODE, 2); in dwb3_program_ogam_lut()
308 REG_SET(DWB_GAMUT_REMAP_MODE, 0, in dwb3_program_gamut_remap()
[all …]
A Ddcn30_optc.c48 REG_SET(OTG_VUPDATE_KEEPOUT, 0, in optc3_triplebuffer_lock()
51 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, in optc3_triplebuffer_lock()
116 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, in optc3_lock()
163 REG_SET(OTG_DRR_V_TOTAL_CHANGE, 0, in optc3_set_vtotal_change_limit()
202 REG_SET(OTG_H_TIMING_CNTL, 0, in optc3_set_odm_bypass()
205 REG_SET(OPTC_MEMORY_CONFIG, 0, in optc3_set_odm_bypass()
244 REG_SET(OPTC_MEMORY_CONFIG, 0, in optc3_set_odm_combine()
264 REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_MODE, opp_cnt - 1); in optc3_set_odm_combine()
A Ddcn30_mpc.c69 REG_SET(DWB_MUX[dwb_id], 0, in mpc3_set_dwb_mux()
79 REG_SET(DWB_MUX[dwb_id], 0, in mpc3_disable_dwb_mux()
340 REG_SET(MPCC_OGAM_MODE[mpcc_id], 0, MPCC_OGAM_MODE, 0); in mpc3_set_output_gamma()
345 REG_SET(MPCC_OGAM_CONTROL[mpcc_id], 0, MPCC_OGAM_MODE, 0); in mpc3_set_output_gamma()
349 REG_SET(MPCC_OGAM_CONTROL[mpcc_id], 0, MPCC_OGAM_MODE, 2); in mpc3_set_output_gamma()
820 REG_SET(MPC_RMU_MEM_PWR_CTRL, 0, in mpc3_power_on_shaper_3dlut()
832 REG_SET(MPC_RMU_MEM_PWR_CTRL, 0, in mpc3_power_on_shaper_3dlut()
1065 REG_SET(MPCC_GAMUT_REMAP_MODE[mpcc_id], 0, in program_gamut_remap()
1110 REG_SET(MPCC_GAMUT_REMAP_MODE[mpcc_id], 0, in program_gamut_remap()
1245 REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode); in mpc3_set_output_csc()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dcn10/
A Ddcn10_mpc.c63 REG_SET(MPCC_BG_R_CR[bottommost_mpcc->mpcc_id], 0, in mpc1_set_bg_color()
65 REG_SET(MPCC_BG_G_Y[bottommost_mpcc->mpcc_id], 0, in mpc1_set_bg_color()
67 REG_SET(MPCC_BG_B_CB[bottommost_mpcc->mpcc_id], 0, in mpc1_set_bg_color()
221 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf); in mpc1_insert_plane()
308 REG_SET(MPCC_BOT_SEL[temp_mpcc->mpcc_id], 0, in mpc1_remove_mpcc()
312 REG_SET(MPCC_BOT_SEL[temp_mpcc->mpcc_id], 0, in mpc1_remove_mpcc()
322 REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf); in mpc1_remove_mpcc()
323 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf); in mpc1_remove_mpcc()
388 REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf); in mpc1_mpc_init_single_inst()
389 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf); in mpc1_mpc_init_single_inst()
[all …]
A Ddcn10_hubp.c598 REG_SET(BLANK_OFFSET_1, 0, in hubp1_program_deadline()
601 REG_SET(DST_DIMENSIONS, 0, in hubp1_program_deadline()
616 REG_SET(NOM_PARAMETERS_0, 0, in hubp1_program_deadline()
620 REG_SET(NOM_PARAMETERS_1, 0, in hubp1_program_deadline()
623 REG_SET(NOM_PARAMETERS_4, 0, in hubp1_program_deadline()
626 REG_SET(NOM_PARAMETERS_5, 0, in hubp1_program_deadline()
637 REG_SET(NOM_PARAMETERS_2, 0, in hubp1_program_deadline()
641 REG_SET(NOM_PARAMETERS_3, 0, in hubp1_program_deadline()
644 REG_SET(NOM_PARAMETERS_6, 0, in hubp1_program_deadline()
647 REG_SET(NOM_PARAMETERS_7, 0, in hubp1_program_deadline()
[all …]
A Ddcn10_dpp_cm.c100 REG_SET(CM_GAMUT_REMAP_CONTROL, 0, in program_gamut_remap()
154 REG_SET( in program_gamut_remap()
201 REG_SET(CM_TEST_DEBUG_INDEX, 0, in dpp1_cm_program_color_matrix()
323 REG_SET(CM_MEM_PWR_CTRL, 0, in dpp1_cm_power_on_regamma_lut()
458 REG_SET(CM_TEST_DEBUG_INDEX, 0, in dpp1_program_input_csc()
491 REG_SET(CM_ICSC_CONTROL, 0, in dpp1_program_input_csc()
579 REG_SET(CM_MEM_PWR_CTRL, 0, in dpp1_power_on_degamma_lut()
678 REG_SET(CM_DGAM_LUT_DATA, 0, in dpp1_program_degamma_lut()
680 REG_SET(CM_DGAM_LUT_DATA, 0, in dpp1_program_degamma_lut()
682 REG_SET(CM_DGAM_LUT_DATA, 0, in dpp1_program_degamma_lut()
[all …]
A Ddcn10_optc.c79 REG_SET(OTG_VSTARTUP_PARAM, 0, in optc1_program_global_sync()
86 REG_SET(OTG_VREADY_PARAM, 0, in optc1_program_global_sync()
94 REG_SET(OTG_STEREO_CONTROL, 0, in optc1_disable_stereo()
188 REG_SET(OTG_H_TOTAL, 0, in optc1_program_timing()
219 REG_SET(OTG_V_TOTAL, 0, in optc1_program_timing()
225 REG_SET(OTG_V_TOTAL_MAX, 0, in optc1_program_timing()
227 REG_SET(OTG_V_TOTAL_MIN, 0, in optc1_program_timing()
940 REG_SET(OTG_V_TOTAL_MAX, 0, in optc1_set_drr()
943 REG_SET(OTG_V_TOTAL_MIN, 0, in optc1_set_drr()
975 REG_SET(OTG_V_TOTAL_MAX, 0, in optc1_set_vtotal_min_max()
[all …]
A Ddcn10_hubbub.c261 REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, 0, in hubbub1_program_urgent_watermarks()
286 REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, 0, in hubbub1_program_urgent_watermarks()
311 REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, 0, in hubbub1_program_urgent_watermarks()
336 REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, 0, in hubbub1_program_urgent_watermarks()
377 REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, 0, in hubbub1_program_stutter_watermarks()
393 REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, 0, in hubbub1_program_stutter_watermarks()
410 REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, 0, in hubbub1_program_stutter_watermarks()
426 REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, 0, in hubbub1_program_stutter_watermarks()
443 REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, 0, in hubbub1_program_stutter_watermarks()
459 REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, 0, in hubbub1_program_stutter_watermarks()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dcn31/
A Ddcn31_hubbub.c177 REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, 0, in hubbub31_program_urgent_watermarks()
187 REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, 0, in hubbub31_program_urgent_watermarks()
231 REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, 0, in hubbub31_program_urgent_watermarks()
275 REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, 0, in hubbub31_program_urgent_watermarks()
319 REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, 0, in hubbub31_program_urgent_watermarks()
882 REG_SET(DCN_VM_FB_LOCATION_BASE, 0, in hubbub31_init_dchub_sys_ctx()
884 REG_SET(DCN_VM_FB_LOCATION_TOP, 0, in hubbub31_init_dchub_sys_ctx()
886 REG_SET(DCN_VM_FB_OFFSET, 0, in hubbub31_init_dchub_sys_ctx()
888 REG_SET(DCN_VM_AGP_BOT, 0, in hubbub31_init_dchub_sys_ctx()
890 REG_SET(DCN_VM_AGP_TOP, 0, in hubbub31_init_dchub_sys_ctx()
[all …]
A Ddcn31_hpo_dp_link_encoder.c214 REG_SET(DP_DPHY_SYM32_TP_CUSTOM0, 0, TP_CUSTOM, tp_custom); in dcn31_hpo_dp_link_enc_set_link_test_pattern()
216 REG_SET(DP_DPHY_SYM32_TP_CUSTOM1, 0, TP_CUSTOM, tp_custom); in dcn31_hpo_dp_link_enc_set_link_test_pattern()
218 REG_SET(DP_DPHY_SYM32_TP_CUSTOM2, 0, TP_CUSTOM, tp_custom); in dcn31_hpo_dp_link_enc_set_link_test_pattern()
220 REG_SET(DP_DPHY_SYM32_TP_CUSTOM3, 0, TP_CUSTOM, tp_custom); in dcn31_hpo_dp_link_enc_set_link_test_pattern()
222 REG_SET(DP_DPHY_SYM32_TP_CUSTOM4, 0, TP_CUSTOM, tp_custom); in dcn31_hpo_dp_link_enc_set_link_test_pattern()
224 REG_SET(DP_DPHY_SYM32_TP_CUSTOM5, 0, TP_CUSTOM, tp_custom); in dcn31_hpo_dp_link_enc_set_link_test_pattern()
226 REG_SET(DP_DPHY_SYM32_TP_CUSTOM6, 0, TP_CUSTOM, tp_custom); in dcn31_hpo_dp_link_enc_set_link_test_pattern()
228 REG_SET(DP_DPHY_SYM32_TP_CUSTOM7, 0, TP_CUSTOM, tp_custom); in dcn31_hpo_dp_link_enc_set_link_test_pattern()
230 REG_SET(DP_DPHY_SYM32_TP_CUSTOM8, 0, TP_CUSTOM, tp_custom); in dcn31_hpo_dp_link_enc_set_link_test_pattern()
232 REG_SET(DP_DPHY_SYM32_TP_CUSTOM9, 0, TP_CUSTOM, tp_custom); in dcn31_hpo_dp_link_enc_set_link_test_pattern()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dcn20/
A Ddcn20_vmid.c75 REG_SET(PAGE_TABLE_START_ADDR_HI32, 0, in dcn20_vmid_setup()
77 REG_SET(PAGE_TABLE_START_ADDR_LO32, 0, in dcn20_vmid_setup()
80 REG_SET(PAGE_TABLE_END_ADDR_HI32, 0, in dcn20_vmid_setup()
82 REG_SET(PAGE_TABLE_END_ADDR_LO32, 0, in dcn20_vmid_setup()
89 REG_SET(PAGE_TABLE_BASE_ADDR_HI32, 0, in dcn20_vmid_setup()
92 REG_SET(PAGE_TABLE_BASE_ADDR_LO32, 0, in dcn20_vmid_setup()
A Ddcn20_optc.c186 REG_SET(OPTC_BYTES_PER_PIXEL, 0, in optc2_set_dsc_config()
214 REG_SET(OPTC_MEMORY_CONFIG, 0, in optc2_set_odm_bypass()
245 REG_SET(OPTC_MEMORY_CONFIG, 0, in optc2_set_odm_combine()
324 REG_SET(OTG_GLOBAL_CONTROL0, 0, in optc2_align_vblanks()
334 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, in optc2_align_vblanks()
362 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, in optc2_align_vblanks()
414 REG_SET(OTG_GLOBAL_CONTROL0, 0, in optc2_align_vblanks()
423 REG_SET(OTG_GLOBAL_CONTROL0, 0, in optc2_triplebuffer_lock()
426 REG_SET(OTG_VUPDATE_KEEPOUT, 0, in optc2_triplebuffer_lock()
445 REG_SET(OTG_VUPDATE_KEEPOUT, 0, in optc2_triplebuffer_unlock()
[all …]
A Ddcn20_hubp.c91 REG_SET(BLANK_OFFSET_1, 0, in hubp2_program_deadline()
94 REG_SET(DST_DIMENSIONS, 0, in hubp2_program_deadline()
109 REG_SET(NOM_PARAMETERS_0, 0, in hubp2_program_deadline()
113 REG_SET(NOM_PARAMETERS_1, 0, in hubp2_program_deadline()
116 REG_SET(NOM_PARAMETERS_4, 0, in hubp2_program_deadline()
119 REG_SET(NOM_PARAMETERS_5, 0, in hubp2_program_deadline()
130 REG_SET(NOM_PARAMETERS_2, 0, in hubp2_program_deadline()
134 REG_SET(NOM_PARAMETERS_3, 0, in hubp2_program_deadline()
137 REG_SET(NOM_PARAMETERS_6, 0, in hubp2_program_deadline()
140 REG_SET(NOM_PARAMETERS_7, 0, in hubp2_program_deadline()
[all …]
A Ddcn20_mpc.c142 REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode); in mpc2_set_output_csc()
182 REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode); in mpc2_set_output_csc()
198 REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode); in mpc2_set_ocsc_default()
241 REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode); in mpc2_set_ocsc_default()
278 REG_SET(MPCC_MEM_PWR_CTRL[mpcc_id], 0, in mpc20_power_on_ogam_lut()
392 REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, in mpc20_program_ogam_pwl()
394 REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, in mpc20_program_ogam_pwl()
396 REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, in mpc20_program_ogam_pwl()
411 REG_SET(MPCC_OGAM_MODE[mpcc_id], 0, MPCC_OGAM_MODE, 0); in apply_DEDCN20_305_wa()
424 REG_SET(MPCC_OGAM_MODE[mpcc_id], 0, MPCC_OGAM_MODE, in apply_DEDCN20_305_wa()
[all …]
A Ddcn20_dpp_cm.c105 REG_SET(CM_DGAM_LUT_DATA, 0, in dpp2_program_degamma_lut()
107 REG_SET(CM_DGAM_LUT_DATA, 0, in dpp2_program_degamma_lut()
109 REG_SET(CM_DGAM_LUT_DATA, 0, in dpp2_program_degamma_lut()
170 REG_SET(CM_GAMUT_REMAP_CONTROL, 0, in program_gamut_remap()
207 REG_SET( in program_gamut_remap()
252 REG_SET(CM_ICSC_CONTROL, 0, CM_ICSC_MODE, 0); in dpp2_program_input_csc()
306 REG_SET(CM_ICSC_CONTROL, 0, in dpp2_program_input_csc()
316 REG_SET(CM_MEM_PWR_CTRL, 0, in dpp20_power_on_blnd_lut()
347 REG_SET(CM_BLNDGAM_LUT_DATA, 0, in dpp20_program_blnd_pwl()
349 REG_SET(CM_BLNDGAM_LUT_DATA, 0, in dpp20_program_blnd_pwl()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dce/
A Ddce_transform.c499 REG_SET(DC_LB_MEMORY_SPLIT, 0, in dce60_transform_set_scaler()
502 REG_SET(DC_LB_MEM_SIZE, 0, in dce60_transform_set_scaler()
1277 REG_SET(OUTPUT_CSC_CONTROL, 0, in configure_graphics_mode()
1282 REG_SET(OUTPUT_CSC_CONTROL, 0, in configure_graphics_mode()
1289 REG_SET(OUTPUT_CSC_CONTROL, 0, in configure_graphics_mode()
1317 REG_SET(OUTPUT_CSC_CONTROL, 0, in configure_graphics_mode()
1322 REG_SET(OUTPUT_CSC_CONTROL, 0, in configure_graphics_mode()
1328 REG_SET(OUTPUT_CSC_CONTROL, 0, in configure_graphics_mode()
1334 REG_SET(OUTPUT_CSC_CONTROL, 0, in configure_graphics_mode()
1343 REG_SET(OUTPUT_CSC_CONTROL, 0, in configure_graphics_mode()
[all …]
A Ddce_ipp.c129 REG_SET(CUR_SURFACE_ADDRESS_HIGH, 0, in dce_ipp_cursor_set_attributes()
132 REG_SET(CUR_SURFACE_ADDRESS, 0, in dce_ipp_cursor_set_attributes()
180 REG_SET(DCFE_MEM_PWR_CTRL, 0, DCP_LUT_MEM_PWR_DIS, 1); in dce_ipp_program_input_lut()
183 REG_SET(DC_LUT_WRITE_EN_MASK, 0, DC_LUT_WRITE_EN_MASK, 0x7); in dce_ipp_program_input_lut()
195 REG_SET(DC_LUT_RW_INDEX, 0, in dce_ipp_program_input_lut()
199 REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR, in dce_ipp_program_input_lut()
202 REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR, in dce_ipp_program_input_lut()
205 REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR, in dce_ipp_program_input_lut()
212 REG_SET(DCFE_MEM_PWR_CTRL, 0, DCP_LUT_MEM_PWR_DIS, 0); in dce_ipp_program_input_lut()
A Ddce_mem_input.c507 REG_SET(GRPH_X_START, 0, in program_size_and_rotation()
510 REG_SET(GRPH_Y_START, 0, in program_size_and_rotation()
513 REG_SET(GRPH_X_END, 0, in program_size_and_rotation()
516 REG_SET(GRPH_Y_END, 0, in program_size_and_rotation()
519 REG_SET(GRPH_PITCH, 0, in program_size_and_rotation()
522 REG_SET(HW_ROTATION, 0, in program_size_and_rotation()
537 REG_SET(GRPH_X_START, 0, in dce60_program_size()
540 REG_SET(GRPH_Y_START, 0, in dce60_program_size()
543 REG_SET(GRPH_X_END, 0, in dce60_program_size()
546 REG_SET(GRPH_Y_END, 0, in dce60_program_size()
[all …]
/linux/arch/arm/mach-imx/
A Danatop.c16 #define REG_SET 0x4 macro
46 REG_SET : REG_CLR; in imx_anatop_enable_weak2p5()
52 regmap_write(anatop, ANADIG_REG_CORE + (enable ? REG_SET : REG_CLR), in imx_anatop_enable_fet_odrive()
58 regmap_write(anatop, ANADIG_REG_2P5 + (enable ? REG_SET : REG_CLR), in imx_anatop_enable_2p5_pulldown()
64 regmap_write(anatop, ANADIG_ANA_MISC0 + (enable ? REG_SET : REG_CLR), in imx_anatop_disconnect_high_snvs()
/linux/drivers/gpu/drm/amd/display/dc/dcn21/
A Ddcn21_hubbub.c113 REG_SET(DCN_VM_FB_LOCATION_BASE, 0, in hubbub21_init_dchub()
115 REG_SET(DCN_VM_FB_LOCATION_TOP, 0, in hubbub21_init_dchub()
117 REG_SET(DCN_VM_FB_OFFSET, 0, in hubbub21_init_dchub()
119 REG_SET(DCN_VM_AGP_BOT, 0, in hubbub21_init_dchub()
121 REG_SET(DCN_VM_AGP_TOP, 0, in hubbub21_init_dchub()
123 REG_SET(DCN_VM_AGP_BASE, 0, in hubbub21_init_dchub()
172 REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, 0, in hubbub21_program_urgent_watermarks()
182 REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, 0, in hubbub21_program_urgent_watermarks()
227 REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, 0, in hubbub21_program_urgent_watermarks()
272 REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, 0, in hubbub21_program_urgent_watermarks()
[all …]
A Ddcn21_hubp.c93 REG_SET(VBLANK_PARAMETERS_5, 0, in apply_DEDCN21_142_wa_for_hostvm_deadline()
101 REG_SET(VBLANK_PARAMETERS_6, 0, in apply_DEDCN21_142_wa_for_hostvm_deadline()
109 REG_SET(FLIP_PARAMETERS_3, 0, in apply_DEDCN21_142_wa_for_hostvm_deadline()
117 REG_SET(FLIP_PARAMETERS_4, 0, in apply_DEDCN21_142_wa_for_hostvm_deadline()
120 REG_SET(FLIP_PARAMETERS_5, 0, in apply_DEDCN21_142_wa_for_hostvm_deadline()
123 REG_SET(FLIP_PARAMETERS_6, 0, in apply_DEDCN21_142_wa_for_hostvm_deadline()
240 REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0, in hubp21_set_vm_system_aperture_settings()
243 REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0, in hubp21_set_vm_system_aperture_settings()
645 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS, 0, in program_surface_flip_and_addr()
654 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0, in program_surface_flip_and_addr()
[all …]
/linux/drivers/thermal/
A Dimx_thermal.c19 #define REG_SET 0x4 macro
225 regmap_write(map, soc_data->panic_alarm_ctrl + REG_SET, in imx_set_panic_temp()
245 regmap_write(map, soc_data->high_alarm_ctrl + REG_SET, in imx_set_alarm_temp()
271 regmap_write(map, soc_data->sensor_ctrl + REG_SET, in imx_get_temp()
289 regmap_write(map, soc_data->sensor_ctrl + REG_SET, in imx_get_temp()
344 regmap_write(map, soc_data->sensor_ctrl + REG_SET, in imx_change_mode()
354 regmap_write(map, soc_data->sensor_ctrl + REG_SET, in imx_change_mode()
738 regmap_write(map, IMX6_MISC0 + REG_SET, in imx_thermal_probe()
740 regmap_write(map, data->socdata->sensor_ctrl + REG_SET, in imx_thermal_probe()
801 regmap_write(map, data->socdata->sensor_ctrl + REG_SET, in imx_thermal_probe()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dcn201/
A Ddcn201_optc.c51 REG_SET(OTG_GLOBAL_CONTROL0, 0, in optc201_triplebuffer_lock()
53 REG_SET(OTG_VUPDATE_KEEPOUT, 0, in optc201_triplebuffer_lock()
55 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, in optc201_triplebuffer_lock()
68 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, in optc201_triplebuffer_unlock()
70 REG_SET(OTG_VUPDATE_KEEPOUT, 0, in optc201_triplebuffer_unlock()

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