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Searched refs:REG_SET_4 (Results 1 – 23 of 23) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dcn20/
A Ddcn20_dpp_cm.c605 REG_SET_4(CM_SHAPER_RAMA_REGION_0_1, 0, in dpp20_program_shaper_luta_settings()
612 REG_SET_4(CM_SHAPER_RAMA_REGION_2_3, 0, in dpp20_program_shaper_luta_settings()
619 REG_SET_4(CM_SHAPER_RAMA_REGION_4_5, 0, in dpp20_program_shaper_luta_settings()
626 REG_SET_4(CM_SHAPER_RAMA_REGION_6_7, 0, in dpp20_program_shaper_luta_settings()
633 REG_SET_4(CM_SHAPER_RAMA_REGION_8_9, 0, in dpp20_program_shaper_luta_settings()
640 REG_SET_4(CM_SHAPER_RAMA_REGION_10_11, 0, in dpp20_program_shaper_luta_settings()
755 REG_SET_4(CM_SHAPER_RAMB_REGION_0_1, 0, in dpp20_program_shaper_lutb_settings()
762 REG_SET_4(CM_SHAPER_RAMB_REGION_2_3, 0, in dpp20_program_shaper_lutb_settings()
769 REG_SET_4(CM_SHAPER_RAMB_REGION_4_5, 0, in dpp20_program_shaper_lutb_settings()
776 REG_SET_4(CM_SHAPER_RAMB_REGION_6_7, 0, in dpp20_program_shaper_lutb_settings()
[all …]
A Ddcn20_stream_encoder.c170 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0, in enc2_stream_encoder_stop_hdmi_info_packets()
180 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0, in enc2_stream_encoder_stop_hdmi_info_packets()
190 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0, in enc2_stream_encoder_stop_hdmi_info_packets()
200 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0, in enc2_stream_encoder_stop_hdmi_info_packets()
247 REG_SET_4(AFMT_GENERIC_HDR, 0, in enc2_update_gsp7_128_info_packet()
A Ddcn20_dsc.c563 REG_SET_4(DSCC_CONFIG0, 0, in dsc_write_to_registers()
575 REG_SET_4(DSCC_INTERRUPT_CONTROL_STATUS, 0, in dsc_write_to_registers()
644 REG_SET_4(DSCC_PPS_CONFIG12, 0, in dsc_write_to_registers()
650 REG_SET_4(DSCC_PPS_CONFIG13, 0, in dsc_write_to_registers()
656 REG_SET_4(DSCC_PPS_CONFIG14, 0, in dsc_write_to_registers()
A Ddcn20_dwb_scl.c706 REG_SET_4(WBSCL_COEF_RAM_TAP_DATA, 0, in wbscl_set_scaler_filter()
A Ddcn20_hubp.c203 REG_SET_4(DCN_EXPANSION_MODE, 0, in hubp2_program_requestor()
/linux/drivers/gpu/drm/amd/display/dc/dcn30/
A Ddcn30_dpp.c896 REG_SET_4(CM_SHAPER_RAMA_REGION_0_1, 0, in dpp3_program_shaper_luta_settings()
903 REG_SET_4(CM_SHAPER_RAMA_REGION_2_3, 0, in dpp3_program_shaper_luta_settings()
910 REG_SET_4(CM_SHAPER_RAMA_REGION_4_5, 0, in dpp3_program_shaper_luta_settings()
917 REG_SET_4(CM_SHAPER_RAMA_REGION_6_7, 0, in dpp3_program_shaper_luta_settings()
924 REG_SET_4(CM_SHAPER_RAMA_REGION_8_9, 0, in dpp3_program_shaper_luta_settings()
931 REG_SET_4(CM_SHAPER_RAMA_REGION_10_11, 0, in dpp3_program_shaper_luta_settings()
1046 REG_SET_4(CM_SHAPER_RAMB_REGION_0_1, 0, in dpp3_program_shaper_lutb_settings()
1053 REG_SET_4(CM_SHAPER_RAMB_REGION_2_3, 0, in dpp3_program_shaper_lutb_settings()
1060 REG_SET_4(CM_SHAPER_RAMB_REGION_4_5, 0, in dpp3_program_shaper_lutb_settings()
1067 REG_SET_4(CM_SHAPER_RAMB_REGION_6_7, 0, in dpp3_program_shaper_lutb_settings()
[all …]
A Ddcn30_mpc.c505 REG_SET_4(SHAPER_RAMA_REGION_0_1[rmu_idx], 0, in mpc3_program_shaper_luta_settings()
512 REG_SET_4(SHAPER_RAMA_REGION_2_3[rmu_idx], 0, in mpc3_program_shaper_luta_settings()
519 REG_SET_4(SHAPER_RAMA_REGION_4_5[rmu_idx], 0, in mpc3_program_shaper_luta_settings()
526 REG_SET_4(SHAPER_RAMA_REGION_6_7[rmu_idx], 0, in mpc3_program_shaper_luta_settings()
533 REG_SET_4(SHAPER_RAMA_REGION_8_9[rmu_idx], 0, in mpc3_program_shaper_luta_settings()
540 REG_SET_4(SHAPER_RAMA_REGION_10_11[rmu_idx], 0, in mpc3_program_shaper_luta_settings()
654 REG_SET_4(SHAPER_RAMB_REGION_0_1[rmu_idx], 0, in mpc3_program_shaper_lutb_settings()
661 REG_SET_4(SHAPER_RAMB_REGION_2_3[rmu_idx], 0, in mpc3_program_shaper_lutb_settings()
669 REG_SET_4(SHAPER_RAMB_REGION_4_5[rmu_idx], 0, in mpc3_program_shaper_lutb_settings()
676 REG_SET_4(SHAPER_RAMB_REGION_6_7[rmu_idx], 0, in mpc3_program_shaper_lutb_settings()
[all …]
A Ddcn30_dio_stream_encoder.c239 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0, in enc3_stream_encoder_stop_hdmi_info_packets()
249 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0, in enc3_stream_encoder_stop_hdmi_info_packets()
259 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0, in enc3_stream_encoder_stop_hdmi_info_packets()
269 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0, in enc3_stream_encoder_stop_hdmi_info_packets()
279 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL6, 0, in enc3_stream_encoder_stop_hdmi_info_packets()
289 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL6, 0, in enc3_stream_encoder_stop_hdmi_info_packets()
299 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL6, 0, in enc3_stream_encoder_stop_hdmi_info_packets()
A Ddcn30_vpg.c88 REG_SET_4(VPG_GENERIC_PACKET_DATA, 0, in vpg3_update_generic_info_packet()
A Ddcn30_cm_common.c92 REG_SET_4(reg_region_cur, 0, in cm_helper_program_gamcor_xfer_func()
/linux/drivers/gpu/drm/amd/display/dc/dcn31/
A Ddcn31_hpo_dp_stream_encoder.c378 REG_SET_4(DP_SYM32_ENC_VID_MSA0, 0, in dcn31_hpo_dp_stream_enc_set_stream_attribute()
384 REG_SET_4(DP_SYM32_ENC_VID_MSA1, 0, in dcn31_hpo_dp_stream_enc_set_stream_attribute()
390 REG_SET_4(DP_SYM32_ENC_VID_MSA2, 0, in dcn31_hpo_dp_stream_enc_set_stream_attribute()
396 REG_SET_4(DP_SYM32_ENC_VID_MSA3, 0, in dcn31_hpo_dp_stream_enc_set_stream_attribute()
402 REG_SET_4(DP_SYM32_ENC_VID_MSA4, 0, in dcn31_hpo_dp_stream_enc_set_stream_attribute()
408 REG_SET_4(DP_SYM32_ENC_VID_MSA5, 0, in dcn31_hpo_dp_stream_enc_set_stream_attribute()
414 REG_SET_4(DP_SYM32_ENC_VID_MSA6, 0, in dcn31_hpo_dp_stream_enc_set_stream_attribute()
420 REG_SET_4(DP_SYM32_ENC_VID_MSA7, 0, in dcn31_hpo_dp_stream_enc_set_stream_attribute()
426 REG_SET_4(DP_SYM32_ENC_VID_MSA8, 0, in dcn31_hpo_dp_stream_enc_set_stream_attribute()
/linux/drivers/gpu/drm/amd/display/dc/dce/
A Ddce_transform.c249 REG_SET_4(SCL_COEF_RAM_TAP_DATA, 0, in program_multi_taps_filter()
1502 REG_SET_4(REGAMMA_CNTLA_REGION_0_1, 0, in regamma_config_regions_and_segments()
1509 REG_SET_4(REGAMMA_CNTLA_REGION_2_3, 0, in regamma_config_regions_and_segments()
1516 REG_SET_4(REGAMMA_CNTLA_REGION_4_5, 0, in regamma_config_regions_and_segments()
1523 REG_SET_4(REGAMMA_CNTLA_REGION_6_7, 0, in regamma_config_regions_and_segments()
1530 REG_SET_4(REGAMMA_CNTLA_REGION_8_9, 0, in regamma_config_regions_and_segments()
1537 REG_SET_4(REGAMMA_CNTLA_REGION_10_11, 0, in regamma_config_regions_and_segments()
1544 REG_SET_4(REGAMMA_CNTLA_REGION_12_13, 0, in regamma_config_regions_and_segments()
1551 REG_SET_4(REGAMMA_CNTLA_REGION_14_15, 0, in regamma_config_regions_and_segments()
A Ddce_stream_encoder.c109 REG_SET_4(AFMT_GENERIC_HDR, 0, in dce110_update_generic_info_packet()
500 REG_SET_4(DP_MSA_TIMING_PARAM3, 0, in dce110_stream_encoder_dp_set_stream_attribute()
A Ddce_i2c_hw.c227 value = REG_SET_4(DC_I2C_DATA, 0, in process_transaction()
/linux/drivers/gpu/drm/amd/display/dc/dcn10/
A Ddcn10_dpp_dscl.c309 REG_SET_4(SCL_COEF_RAM_TAP_DATA, 0, in dpp1_dscl_set_scaler_filter()
597 REG_SET_4(SCL_TAP_CONTROL, 0, in dpp1_dscl_set_scaler_auto_scale()
786 REG_SET_4(SCL_TAP_CONTROL, 0, in dpp1_dscl_set_scaler_manual_scale()
A Ddcn10_stream_encoder.c100 REG_SET_4(AFMT_GENERIC_HDR, 0, in enc1_update_generic_info_packet()
459 REG_SET_4(DP_MSA_TIMING_PARAM3, 0, in enc1_stream_encoder_dp_set_stream_attribute()
826 REG_SET_4(AFMT_GENERIC_HDR, 0, in enc1_stream_encoder_send_immediate_sdp_message()
A Ddcn10_optc.c797 REG_SET_4(OTG_TRIGA_CNTL, 0, in optc1_enable_crtc_reset()
1221 REG_SET_4(OTG_TEST_PATTERN_CONTROL, 0, in optc1_set_test_pattern()
A Ddcn10_cm_common.c115 REG_SET_4(reg_region_cur, 0, in cm_helper_program_xfer_func()
A Ddcn10_hubp.c560 REG_SET_4(DCN_EXPANSION_MODE, 0, in hubp1_program_requestor()
/linux/drivers/gpu/drm/amd/display/dc/dcn201/
A Ddcn201_hubp.c75 REG_SET_4(DCN_EXPANSION_MODE, 0, in hubp201_program_requestor()
/linux/drivers/gpu/drm/amd/display/dmub/src/
A Ddmub_reg.h76 #define REG_SET_4(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4) \ macro
/linux/drivers/gpu/drm/amd/display/dc/dcn21/
A Ddcn21_hubp.c145 REG_SET_4(DCN_EXPANSION_MODE, 0, in hubp21_program_requestor()
/linux/drivers/gpu/drm/amd/display/dc/inc/
A Dreg_helper.h78 #define REG_SET_4(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4) \ macro

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