| /linux/drivers/gpu/drm/amd/display/dc/dcn31/ |
| A D | dcn31_dccg.c | 185 REG_UPDATE_2(SYMCLK32_SE_CNTL, in dccg31_enable_symclk32_se() 193 REG_UPDATE_2(SYMCLK32_SE_CNTL, in dccg31_enable_symclk32_se() 201 REG_UPDATE_2(SYMCLK32_SE_CNTL, in dccg31_enable_symclk32_se() 209 REG_UPDATE_2(SYMCLK32_SE_CNTL, in dccg31_enable_symclk32_se() 228 REG_UPDATE_2(SYMCLK32_SE_CNTL, in dccg31_disable_symclk32_se() 236 REG_UPDATE_2(SYMCLK32_SE_CNTL, in dccg31_disable_symclk32_se() 244 REG_UPDATE_2(SYMCLK32_SE_CNTL, in dccg31_disable_symclk32_se() 252 REG_UPDATE_2(SYMCLK32_SE_CNTL, in dccg31_disable_symclk32_se() 280 REG_UPDATE_2(SYMCLK32_LE_CNTL, in dccg31_enable_symclk32_le() 288 REG_UPDATE_2(SYMCLK32_LE_CNTL, in dccg31_enable_symclk32_le() [all …]
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| A D | dcn31_vpg.c | 59 REG_UPDATE_2(VPG_MEM_PWR, VPG_GSP_MEM_LIGHT_SLEEP_DIS, 0, VPG_GSP_LIGHT_SLEEP_FORCE, 1); in vpg31_powerdown() 69 REG_UPDATE_2(VPG_MEM_PWR, VPG_GSP_MEM_LIGHT_SLEEP_DIS, 1, VPG_GSP_LIGHT_SLEEP_FORCE, 0); in vpg31_poweron()
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| A D | dcn31_afmt.c | 64 REG_UPDATE_2(AFMT_MEM_PWR, AFMT_MEM_PWR_DIS, 0, AFMT_MEM_PWR_FORCE, 1); in afmt31_powerdown() 74 REG_UPDATE_2(AFMT_MEM_PWR, AFMT_MEM_PWR_DIS, 1, AFMT_MEM_PWR_FORCE, 0); in afmt31_poweron()
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| A D | dcn31_optc.c | 113 REG_UPDATE_2(OTG_CONTROL, in optc31_enable_crtc() 149 REG_UPDATE_2(OTG_CONTROL, in optc31_immediate_disable_crtc() 179 REG_UPDATE_2(OTG_V_TOTAL_CONTROL, in optc31_set_drr()
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| A D | dcn31_hpo_dp_link_encoder.c | 306 REG_UPDATE_2(DP_DPHY_SYM32_SAT_VC0, in dcn31_hpo_dp_link_enc_update_stream_allocation_table() 320 REG_UPDATE_2(DP_DPHY_SYM32_SAT_VC1, in dcn31_hpo_dp_link_enc_update_stream_allocation_table() 334 REG_UPDATE_2(DP_DPHY_SYM32_SAT_VC2, in dcn31_hpo_dp_link_enc_update_stream_allocation_table() 348 REG_UPDATE_2(DP_DPHY_SYM32_SAT_VC3, in dcn31_hpo_dp_link_enc_update_stream_allocation_table()
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| A D | dcn31_hpo_dp_stream_encoder.c | 131 REG_UPDATE_2(DP_SYM32_ENC_VID_CRC_CONTROL, in dcn31_hpo_dp_stream_enc_dp_unblank() 561 REG_UPDATE_2(DP_SYM32_ENC_VID_VBID_CONTROL, in dcn31_hpo_dp_stream_enc_set_dsc_pps_info_packet() 572 REG_UPDATE_2(DP_SYM32_ENC_SDP_GSP_CONTROL11, in dcn31_hpo_dp_stream_enc_set_dsc_pps_info_packet() 639 REG_UPDATE_2(DP_SYM32_ENC_SDP_AUDIO_CONTROL0, in dcn31_hpo_dp_stream_enc_audio_enable()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn30/ |
| A D | dcn30_dio_stream_encoder.c | 101 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0, in enc3_update_hdmi_info_packet() 108 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0, in enc3_update_hdmi_info_packet() 328 REG_UPDATE_2(DP_DSC_CNTL, in enc3_dp_set_dsc_config() 379 REG_UPDATE_2(DP_MSA_VBID_MISC, in enc3_dp_set_dsc_pps_info_packet() 597 REG_UPDATE_2(HDMI_CONTROL, in enc3_stream_encoder_hdmi_set_stream_attribute() 601 REG_UPDATE_2(HDMI_CONTROL, in enc3_stream_encoder_hdmi_set_stream_attribute() 608 REG_UPDATE_2(HDMI_CONTROL, in enc3_stream_encoder_hdmi_set_stream_attribute() 612 REG_UPDATE_2(HDMI_CONTROL, in enc3_stream_encoder_hdmi_set_stream_attribute() 618 REG_UPDATE_2(HDMI_CONTROL, in enc3_stream_encoder_hdmi_set_stream_attribute() 631 REG_UPDATE_2(HDMI_CONTROL, in enc3_stream_encoder_hdmi_set_stream_attribute() [all …]
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| A D | dcn30_afmt.c | 59 REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2, in afmt3_setup_hdmi_audio() 66 REG_UPDATE_2(AFMT_60958_0, in afmt3_setup_hdmi_audio() 183 REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2, in afmt3_setup_dp_audio()
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| A D | dcn30_optc.c | 75 REG_UPDATE_2(OTG_GLOBAL_CONTROL1, in optc3_lock_doublebuffer_enable() 78 REG_UPDATE_2(OTG_GLOBAL_CONTROL4, in optc3_lock_doublebuffer_enable() 99 REG_UPDATE_2(OTG_GLOBAL_CONTROL0, in optc3_lock_doublebuffer_disable() 102 REG_UPDATE_2(OTG_GLOBAL_CONTROL1, in optc3_lock_doublebuffer_disable()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn10/ |
| A D | dcn10_opp.c | 79 REG_UPDATE_2(FMT_CONTROL, in opp1_set_spatial_dither() 83 REG_UPDATE_2(FMT_CONTROL, in opp1_set_spatial_dither() 90 REG_UPDATE_2(FMT_CONTROL, in opp1_set_spatial_dither() 197 REG_UPDATE_2(FMT_CLAMP_CNTL, in opp1_set_clamping() 203 REG_UPDATE_2(FMT_CLAMP_CNTL, in opp1_set_clamping() 208 REG_UPDATE_2(FMT_CLAMP_CNTL, in opp1_set_clamping() 213 REG_UPDATE_2(FMT_CLAMP_CNTL, in opp1_set_clamping() 219 REG_UPDATE_2(FMT_CLAMP_CNTL, in opp1_set_clamping() 239 REG_UPDATE_2(FMT_DYNAMIC_EXP_CNTL, in opp1_set_dyn_expansion() 254 REG_UPDATE_2(FMT_DYNAMIC_EXP_CNTL, in opp1_set_dyn_expansion() [all …]
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| A D | dcn10_optc.c | 192 REG_UPDATE_2(OTG_H_SYNC_A, in optc1_program_timing() 206 REG_UPDATE_2(OTG_H_BLANK_START_END, in optc1_program_timing() 233 REG_UPDATE_2(OTG_V_SYNC_A, in optc1_program_timing() 281 REG_UPDATE_2(OTG_CONTROL, in optc1_program_timing() 368 REG_UPDATE_2(CONTROL, in optc1_set_vtg_params() 410 REG_UPDATE_2(OTG_BLANK_CONTROL, in optc1_unblank_crtc() 433 REG_UPDATE_2(OTG_BLANK_CONTROL, in optc1_blank_crtc() 476 REG_UPDATE_2(OTG_CLOCK_CONTROL, in optc1_enable_optc_clock() 483 REG_UPDATE_2(OTG_CLOCK_CONTROL, in optc1_enable_optc_clock() 518 REG_UPDATE_2(OTG_CONTROL, in optc1_enable_crtc() [all …]
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| A D | dcn10_stream_encoder.c | 347 REG_UPDATE_2(DP_PIXEL_FORMAT, in enc1_stream_encoder_dp_set_stream_attribute() 532 REG_UPDATE_2(HDMI_CONTROL, in enc1_stream_encoder_hdmi_set_stream_attribute() 538 REG_UPDATE_2(HDMI_CONTROL, in enc1_stream_encoder_hdmi_set_stream_attribute() 547 REG_UPDATE_2(HDMI_CONTROL, in enc1_stream_encoder_hdmi_set_stream_attribute() 553 REG_UPDATE_2(HDMI_CONTROL, in enc1_stream_encoder_hdmi_set_stream_attribute() 561 REG_UPDATE_2(HDMI_CONTROL, in enc1_stream_encoder_hdmi_set_stream_attribute() 576 REG_UPDATE_2(HDMI_CONTROL, in enc1_stream_encoder_hdmi_set_stream_attribute() 588 REG_UPDATE_2(HDMI_CONTROL, in enc1_stream_encoder_hdmi_set_stream_attribute() 1001 REG_UPDATE_2(DP_VID_TIMING, in enc1_stream_encoder_dp_unblank() 1312 REG_UPDATE_2(AFMT_60958_0, in enc1_se_setup_hdmi_audio() [all …]
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| A D | dcn10_hubp.c | 46 REG_UPDATE_2(DCHUBP_CNTL, in hubp1_set_blank() 195 REG_UPDATE_2(DCSURF_SURFACE_PITCH, in hubp1_program_size() 199 REG_UPDATE_2(DCSURF_SURFACE_PITCH_C, in hubp1_program_size() 219 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, in hubp1_program_rotation() 223 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, in hubp1_program_rotation() 227 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, in hubp1_program_rotation() 231 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, in hubp1_program_rotation() 254 REG_UPDATE_2(HUBPRET_CONTROL, in hubp1_program_pixel_format() 332 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, in hubp1_program_pixel_format() 337 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, in hubp1_program_pixel_format() [all …]
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| A D | dcn10_link_encoder.c | 272 REG_UPDATE_2(DP_DPHY_PRBS_CNTL, in set_dp_phy_pattern_symbol_error() 292 REG_UPDATE_2(DP_DPHY_PRBS_CNTL, in set_dp_phy_pattern_prbs7() 531 REG_UPDATE_2(DP_SEC_CNTL1, in dcn10_psr_program_secondary_packet() 1252 REG_UPDATE_2(DP_MSE_SAT0, in dcn10_link_encoder_update_mst_stream_allocation_table() 1266 REG_UPDATE_2(DP_MSE_SAT0, in dcn10_link_encoder_update_mst_stream_allocation_table() 1280 REG_UPDATE_2(DP_MSE_SAT1, in dcn10_link_encoder_update_mst_stream_allocation_table() 1294 REG_UPDATE_2(DP_MSE_SAT1, in dcn10_link_encoder_update_mst_stream_allocation_table()
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| /linux/drivers/gpu/drm/amd/display/dc/dce/ |
| A D | dce_opp.c | 158 REG_UPDATE_2(FMT_BIT_DEPTH_CONTROL, in dce60_set_truncation() 179 REG_UPDATE_2(FMT_BIT_DEPTH_CONTROL, in dce60_set_truncation() 229 REG_UPDATE_2(FMT_CONTROL, in set_spatial_dither() 233 REG_UPDATE_2(FMT_CONTROL, in set_spatial_dither() 239 REG_UPDATE_2(FMT_CONTROL, in set_spatial_dither() 313 REG_UPDATE_2(FMT_BIT_DEPTH_CONTROL, in set_temporal_dither() 483 REG_UPDATE_2(FMT_CONTROL, in set_pixel_encoding() 488 REG_UPDATE_2(FMT_CONTROL, in set_pixel_encoding() 514 REG_UPDATE_2(FMT_CONTROL, in dce60_set_pixel_encoding() 526 REG_UPDATE_2(FMT_CONTROL, in dce60_set_pixel_encoding() [all …]
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| A D | dce_stream_encoder.c | 135 REG_UPDATE_2(AFMT_VBI_PACKET_CONTROL, in dce110_update_generic_info_packet() 452 REG_UPDATE_2( in dce110_stream_encoder_dp_set_stream_attribute() 595 REG_UPDATE_2(HDMI_CONTROL, in dce110_stream_encoder_hdmi_set_stream_attribute() 599 REG_UPDATE_2(HDMI_CONTROL, in dce110_stream_encoder_hdmi_set_stream_attribute() 606 REG_UPDATE_2(HDMI_CONTROL, in dce110_stream_encoder_hdmi_set_stream_attribute() 610 REG_UPDATE_2(HDMI_CONTROL, in dce110_stream_encoder_hdmi_set_stream_attribute() 616 REG_UPDATE_2(HDMI_CONTROL, in dce110_stream_encoder_hdmi_set_stream_attribute() 630 REG_UPDATE_2(HDMI_CONTROL, in dce110_stream_encoder_hdmi_set_stream_attribute() 642 REG_UPDATE_2(HDMI_CONTROL, in dce110_stream_encoder_hdmi_set_stream_attribute() 1343 REG_UPDATE_2(AFMT_60958_0, in dce110_se_setup_hdmi_audio() [all …]
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| A D | dce_mem_input.c | 158 REG_UPDATE_2(DVMM_PTE_ARB_CONTROL, in dce_mi_program_pte_vm() 287 REG_UPDATE_2(DPG_PIPE_STUTTER_CONTROL2, in dce120_program_stutter_watermark() 291 REG_UPDATE_2(DPG_PIPE_STUTTER_CONTROL, in dce120_program_stutter_watermark() 328 REG_UPDATE_2(DPG_PIPE_STUTTER_CONTROL, in dce_mi_program_display_marks() 355 REG_UPDATE_2(DPG_PIPE_STUTTER_CONTROL, in dce60_mi_program_display_marks() 385 REG_UPDATE_2(DPG_PIPE_STUTTER_CONTROL, in dce112_mi_program_display_marks() 418 REG_UPDATE_2(DPG_PIPE_STUTTER_CONTROL, in dce120_mi_program_display_marks() 619 REG_UPDATE_2(GRPH_CONTROL, in program_grph_pixel_format()
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| A D | dce_abm.c | 73 REG_UPDATE_2(MASTER_COMM_CMD_REG, in dce_abm_set_pipe() 167 REG_UPDATE_2(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, in dce_abm_init() 210 REG_UPDATE_2(MASTER_COMM_CMD_REG, in dce_abm_set_level()
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| A D | dce_hwseq.c | 186 REG_UPDATE_2(PHYPLL_PIXEL_RATE_CNTL[tg_inst], in dce_crtc_switch_to_clk_src() 196 REG_UPDATE_2(PIXEL_RATE_CNTL[tg_inst], in dce_crtc_switch_to_clk_src()
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| A D | dce_dmcu.c | 92 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, in dce_dmcu_load_iram() 104 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, in dce_dmcu_load_iram() 343 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, in dcn10_get_dmcu_version() 358 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, in dcn10_get_dmcu_version() 493 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, in dcn10_dmcu_load_iram() 505 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, in dcn10_dmcu_load_iram()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn20/ |
| A D | dcn20_stream_encoder.c | 82 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0, in enc2_update_hdmi_info_packet() 89 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0, in enc2_update_hdmi_info_packet() 96 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0, in enc2_update_hdmi_info_packet() 103 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0, in enc2_update_hdmi_info_packet() 110 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0, in enc2_update_hdmi_info_packet() 270 REG_UPDATE_2(AFMT_VBI_PACKET_CONTROL1, in enc2_update_gsp7_128_info_packet() 287 REG_UPDATE_2(DP_DSC_CNTL, in enc2_dp_set_dsc_config() 326 REG_UPDATE_2(DP_MSA_VBID_MISC, in enc2_dp_set_dsc_pps_info_packet() 337 REG_UPDATE_2(DP_SEC_CNTL, in enc2_dp_set_dsc_pps_info_packet() 385 REG_UPDATE_2(DME_CONTROL, in enc2_set_dynamic_metadata() [all …]
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| A D | dcn20_optc.c | 65 REG_UPDATE_2(OTG_CONTROL, in optc2_enable_crtc() 355 REG_UPDATE_2(OTG_GLOBAL_CONTROL1, in optc2_align_vblanks() 401 REG_UPDATE_2(OTG_GLOBAL_CONTROL1, in optc2_align_vblanks() 458 REG_UPDATE_2(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 1, in optc2_lock_doublebuffer_enable() 465 REG_UPDATE_2(OTG_GLOBAL_CONTROL1, in optc2_lock_doublebuffer_enable() 481 REG_UPDATE_2(OTG_GLOBAL_CONTROL1, in optc2_lock_doublebuffer_disable() 487 REG_UPDATE_2(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 0, in optc2_lock_doublebuffer_disable()
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| A D | dcn20_opp.c | 227 REG_UPDATE_2(DPG_CONTROL, in opp2_set_disp_pattern_generator() 238 REG_UPDATE_2(DPG_CONTROL, in opp2_set_disp_pattern_generator() 249 REG_UPDATE_2(DPG_CONTROL, in opp2_set_disp_pattern_generator() 278 REG_UPDATE_2(DPG_CONTROL, in opp2_set_disp_pattern_generator()
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| A D | dcn20_hubp.c | 364 REG_UPDATE_2(DCSURF_SURFACE_PITCH, in hubp2_program_size() 371 REG_UPDATE_2(DCSURF_SURFACE_PITCH_C, in hubp2_program_size() 391 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, in hubp2_program_rotation() 395 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, in hubp2_program_rotation() 399 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, in hubp2_program_rotation() 403 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, in hubp2_program_rotation() 440 REG_UPDATE_2(HUBPRET_CONTROL, in hubp2_program_pixel_format() 518 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, in hubp2_program_pixel_format() 523 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, in hubp2_program_pixel_format() 606 REG_UPDATE_2(CURSOR_SIZE, in hubp2_cursor_set_attributes() [all …]
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| A D | dcn20_dccg.c | 113 REG_UPDATE_2(OTG_PIXEL_RATE_CNTL[otg_inst], in dccg2_otg_add_pixel() 125 REG_UPDATE_2(OTG_PIXEL_RATE_CNTL[otg_inst], in dccg2_otg_drop_pixel()
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