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Searched refs:SDMA0 (Results 1 – 12 of 12) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
A Dsdma_v4_4.c60 { "SDMA_MBANK_DATA_BUF0_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
64 { "SDMA_MBANK_DATA_BUF1_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
68 { "SDMA_MBANK_DATA_BUF2_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
72 { "SDMA_MBANK_DATA_BUF3_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
76 { "SDMA_MBANK_DATA_BUF4_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
80 { "SDMA_MBANK_DATA_BUF5_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
84 { "SDMA_MBANK_DATA_BUF6_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
124 { "SDMA_UCODE_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER2),
128 { "SDMA_RB_CMD_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER2),
132 { "SDMA_IB_CMD_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER2),
[all …]
A Dsdma_v4_0.c1352 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); in sdma_v4_1_update_power_gating()
1356 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); in sdma_v4_1_update_power_gating()
1359 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); in sdma_v4_1_update_power_gating()
1362 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); in sdma_v4_1_update_power_gating()
1371 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); in sdma_v4_1_init_power_gating()
1374 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); in sdma_v4_1_init_power_gating()
1377 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); in sdma_v4_1_init_power_gating()
1380 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); in sdma_v4_1_init_power_gating()
1390 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); in sdma_v4_1_init_power_gating()
2385 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL)); in sdma_v4_0_get_clockgating_state()
[all …]
A Damdgpu_amdkfd_gfx_v10_3.c155 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0, in get_sdma_rlc_reg_offset()
159 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0, in get_sdma_rlc_reg_offset()
163 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0, in get_sdma_rlc_reg_offset()
167 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0, in get_sdma_rlc_reg_offset()
A Damdgpu_amdkfd_arcturus.c84 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0, in get_sdma_rlc_reg_offset()
A Damdgpu_amdkfd_gfx_v10.c178 SOC15_REG_OFFSET(SDMA0, 0, in get_sdma_rlc_reg_offset()
A Damdgpu_amdkfd_gfx_v9.c208 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0, in get_sdma_rlc_reg_offset()
A Dnv.c402 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
A Dsdma_v2_4.c285 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1); in sdma_v2_4_ring_emit_hdp_flush()
A Dsoc15.c418 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
A Dsdma_v3_0.c459 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1); in sdma_v3_0_ring_emit_hdp_flush()
/linux/drivers/gpu/drm/radeon/
A Dcik_sdma.c177 ref_and_mask = SDMA0; in cik_sdma_hdp_flush_ring_emit()
A Dcikd.h860 #define SDMA0 (1 << 10) macro

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