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Searched refs:SDMA0_HWIP (Results 1 – 11 of 11) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
A Damdgpu_discovery.c158 [SDMA0_HWIP] = SDMA0_HWID,
864 switch (adev->ip_versions[SDMA0_HWIP][0]) { in amdgpu_discovery_set_sdma_ip_blocks()
892 adev->ip_versions[SDMA0_HWIP][0]); in amdgpu_discovery_set_sdma_ip_blocks()
1006 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 0); in amdgpu_discovery_set_ip_blocks()
1027 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 1); in amdgpu_discovery_set_ip_blocks()
1086 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 0); in amdgpu_discovery_set_ip_blocks()
1109 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 2); in amdgpu_discovery_set_ip_blocks()
1136 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 4, 0); in amdgpu_discovery_set_ip_blocks()
1137 adev->ip_versions[SDMA0_HWIP][1] = IP_VERSION(4, 4, 0); in amdgpu_discovery_set_ip_blocks()
1138 adev->ip_versions[SDMA0_HWIP][2] = IP_VERSION(4, 4, 0); in amdgpu_discovery_set_ip_blocks()
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A Dsdma_v4_0.c399 return (adev->reg_offset[SDMA0_HWIP][0][0] + offset); in sdma_v4_0_get_reg_offset()
472 switch (adev->ip_versions[SDMA0_HWIP][0]) { in sdma_v4_0_init_golden_registers()
542 switch (adev->ip_versions[SDMA0_HWIP][0]) { in sdma_v4_0_setup_ulv()
594 adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 4, 0)) in sdma_v4_0_destroy_inst_ctx()
624 switch (adev->ip_versions[SDMA0_HWIP][0]) { in sdma_v4_0_init_microcode()
1398 switch (adev->ip_versions[SDMA0_HWIP][0]) { in sdma_v4_0_init_pg()
1841 switch (adev->ip_versions[SDMA0_HWIP][0]) { in sdma_v4_0_fw_support_paging_queue()
2139 if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 0)) in sdma_v4_0_process_trap_irq()
2146 if (adev->ip_versions[SDMA0_HWIP][0] != IP_VERSION(4, 2, 0)) in sdma_v4_0_process_trap_irq()
2362 switch (adev->ip_versions[SDMA0_HWIP][0]) { in sdma_v4_0_set_powergating_state()
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A Ddimgrey_cavefish_reg_init.c46 adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in dimgrey_cavefish_reg_base_init()
A Daldebaran_reg_init.c43 adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(SDMA0_BASE.instance[i])); in aldebaran_reg_base_init()
A Darct_reg_init.c44 adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(SDMA0_BASE.instance[i])); in arct_reg_base_init()
A Dvega10_reg_init.c47 adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(SDMA0_BASE.instance[i])); in vega10_reg_base_init()
A Dsdma_v4_4.c40 uint32_t sdma_base = adev->reg_offset[SDMA0_HWIP][0][0]; in sdma_v4_4_get_reg_offset()
A Dvega20_reg_init.c46 adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(SDMA0_BASE.instance[i])); in vega20_reg_base_init()
A Dsdma_v5_2.c139 switch (adev->ip_versions[SDMA0_HWIP][0]) { in sdma_v5_2_init_microcode()
177 if (amdgpu_sriov_vf(adev) && (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 2, 0))) in sdma_v5_2_init_microcode()
1541 …if (adev->sdma.instance[i].fw_version < 70 && adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 2,… in sdma_v5_2_update_medium_grain_clock_gating()
1578 …if (adev->sdma.instance[i].fw_version < 70 && adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 2,… in sdma_v5_2_update_medium_grain_light_sleep()
1607 switch (adev->ip_versions[SDMA0_HWIP][0]) { in sdma_v5_2_set_clockgating_state()
A Dsdma_v5_0.c190 switch (adev->ip_versions[SDMA0_HWIP][0]) { in sdma_v5_0_init_golden_registers()
251 if (amdgpu_sriov_vf(adev) && (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 0, 5))) in sdma_v5_0_init_microcode()
256 switch (adev->ip_versions[SDMA0_HWIP][0]) { in sdma_v5_0_init_microcode()
1637 switch (adev->ip_versions[SDMA0_HWIP][0]) { in sdma_v5_0_set_clockgating_state()
A Damdgpu.h732 SDMA0_HWIP, enumerator

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