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Searched refs:SF (Results 1 – 25 of 48) sorted by relevance

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/linux/drivers/gpu/drm/amd/display/dc/dcn30/
A Ddcn30_mmhubbub.h241 SF(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK, mask_sh),\
293 SF(MCIF_WB_BUF_PITCH, MCIF_WB_BUF_LUMA_PITCH, mask_sh),\
300 SF(MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_MODE, mask_sh),\
307 SF(MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_TMZ, mask_sh),\
315 SF(MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_MODE, mask_sh),\
322 SF(MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_TMZ, mask_sh),\
330 SF(MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_MODE, mask_sh),\
337 SF(MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_TMZ, mask_sh),\
345 SF(MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_MODE, mask_sh),\
352 SF(MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_TMZ, mask_sh),\
[all …]
A Ddcn30_optc.h128 SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\
134 SF(OTG0_OTG_V_TOTAL, OTG_V_TOTAL, mask_sh),\
141 SF(OTG0_OTG_CONTROL, OTG_MASTER_EN, mask_sh),\
145 SF(OTG0_OTG_CONTROL, OTG_OUT_MUX, mask_sh),\
178 SF(OTG0_OTG_STATUS, OTG_V_BLANK, mask_sh),\
207 SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\
208 SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\
209 SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\
221 SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\
223 SF(OTG0_OTG_CRC0_DATA_RG, CRC0_G_Y, mask_sh),\
[all …]
A Ddcn30_mpc.h292 SF(MPCC0_MPCC_CONTROL, MPCC_BG_BPC, mask_sh),\
297 SF(MPC_OUT0_CSC_MODE, MPC_OCSC_MODE, mask_sh),\
316 SF(MPC_DWB0_MUX, MPC_DWB0_MUX, mask_sh),\
322 SF(MPC_RMU_CONTROL, MPC_RMU0_MUX, mask_sh), \
323 SF(MPC_RMU_CONTROL, MPC_RMU1_MUX, mask_sh), \
399 SF(MPCC0_MPCC_CONTROL, MPCC_BG_BPC, mask_sh),\
424 SF(MPC_DWB0_MUX, MPC_DWB0_MUX, mask_sh),\
430 SF(MPC_RMU_CONTROL, MPC_RMU0_MUX, mask_sh), \
431 SF(MPC_RMU_CONTROL, MPC_RMU1_MUX, mask_sh), \
615 SF(MPC_DWB0_MUX, MPC_DWB0_MUX, mask_sh),\
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dcn31/
A Ddcn31_optc.h119 SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\
125 SF(OTG0_OTG_V_TOTAL, OTG_V_TOTAL, mask_sh),\
132 SF(OTG0_OTG_CONTROL, OTG_MASTER_EN, mask_sh),\
136 SF(OTG0_OTG_CONTROL, OTG_OUT_MUX, mask_sh),\
168 SF(OTG0_OTG_STATUS, OTG_V_BLANK, mask_sh),\
191 SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\
192 SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\
193 SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\
205 SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\
207 SF(OTG0_OTG_CRC0_DATA_RG, CRC0_G_Y, mask_sh),\
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dcn20/
A Ddcn20_mmhubbub.h104 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_P_VMID, mask_sh),\
114 SF(MCIF_WB0_MCIF_WB_BUF_PITCH, MCIF_WB_BUF_LUMA_PITCH, mask_sh),\
121 SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_MODE, mask_sh),\
124 SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_FIELD, mask_sh),\
133 SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_TMZ, mask_sh),\
141 SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_MODE, mask_sh),\
153 SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_TMZ, mask_sh),\
161 SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_MODE, mask_sh),\
173 SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_TMZ, mask_sh),\
254 SF(WBIF0_SMU_WM_CONTROL, MCIF_WB0_WM_CHG_SEL, mask_sh),\
[all …]
A Ddcn20_dwb.h53 #define SF(reg_name, field_name, post_fix)\ macro
106 SF(WB_ENABLE, WB_ENABLE, mask_sh),\
111 SF(WB_EC_CONFIG, WB_LB_LS_DIS, mask_sh),\
112 SF(WB_EC_CONFIG, WB_LB_SD_DIS, mask_sh),\
120 SF(CNV_MODE, CNV_OUT_BPC, mask_sh),\
123 SF(CNV_MODE, CNV_STEREO_TYPE, mask_sh),\
129 SF(CNV_MODE, CNV_NEW_CONTENT, mask_sh),\
154 SF(WB_DBG_MODE, WB_DBG_CMAP, mask_sh),\
157 SF(WB_HW_DEBUG, WB_HW_DEBUG, mask_sh),\
169 SF(WBSCL_MODE, WBSCL_MODE, mask_sh),\
[all …]
A Ddcn20_optc.h54 SF(OTG0_OTG_GLOBAL_CONTROL2, DIG_UPDATE_LOCATION, mask_sh),\
57 SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_END_X, mask_sh), \
59 SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_END_Y, mask_sh),\
60 SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_MODE, mask_sh), \
64 SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DSC_MODE, mask_sh),\
67 SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_FORMAT, mask_sh),\
71 SF(ODM0_OPTC_MEMORY_CONFIG, OPTC_MEM_SEL, mask_sh),\
73 SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DSC_MODE, mask_sh),\
76 SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_SEGMENT_WIDTH, mask_sh),\
77 SF(DWB_SOURCE_SELECT, OPTC_DWB0_SOURCE_SELECT, mask_sh),\
[all …]
A Ddcn20_mpc.h138 SF(MPCC0_MPCC_CONTROL, MPCC_BG_BPC, mask_sh),\
139 SF(MPCC0_MPCC_CONTROL, MPCC_BOT_GAIN_MODE, mask_sh),\
140 SF(MPCC0_MPCC_TOP_GAIN, MPCC_TOP_GAIN, mask_sh),\
144 SF(MPC_OUT0_CSC_MODE, MPC_OCSC_MODE, mask_sh),\
145 SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C11_A, mask_sh),\
146 SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C12_A, mask_sh),\
147 SF(MPCC0_MPCC_STATUS, MPCC_DISABLED, mask_sh),\
169 SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_DIS, mask_sh),\
175 SF(MPCC_OGAM0_MPCC_OGAM_MODE, MPCC_OGAM_MODE, mask_sh),\
176 SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_MODE, mask_sh),\
[all …]
A Ddcn20_vmid.h47 SF(DCN_VM_CONTEXT0_CNTL, VM_CONTEXT0_PAGE_TABLE_DEPTH, mask_sh),\
48 SF(DCN_VM_CONTEXT0_CNTL, VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE, mask_sh),\
49 SF(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32, mask_sh),\
50 SF(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32, mask_sh),\
51 …SF(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4, mask_sh)…
52 …SF(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32, mask_sh…
53 SF(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4, mask_sh),\
54 SF(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32, mask_sh)
/linux/drivers/gpu/drm/amd/display/dc/dcn10/
A Ddcn10_optc.h201 SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\
208 SF(OTG0_OTG_V_TOTAL, OTG_V_TOTAL, mask_sh),\
215 SF(OTG0_OTG_CONTROL, OTG_MASTER_EN, mask_sh),\
255 SF(OTG0_OTG_STATUS, OTG_V_BLANK, mask_sh),\
263 SF(OTG0_OTG_CLOCK_CONTROL, OTG_BUSY, mask_sh),\
279 SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\
280 SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\
281 SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\
294 SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\
296 SF(OTG0_OTG_CRC0_DATA_RG, CRC0_G_Y, mask_sh),\
[all …]
A Ddcn10_dwb.h49 #define SF(reg_name, field_name, post_fix)\ macro
87 SF(CNV0_WB_ENABLE, WB_ENABLE, mask_sh),\
91 SF(CNV0_WB_EC_CONFIG, WB_LB_LS_DIS, mask_sh),\
92 SF(CNV0_WB_EC_CONFIG, WB_LUT_LS_DIS, mask_sh),\
93 SF(CNV0_CNV_MODE, CNV_WINDOW_CROP_EN, mask_sh),\
94 SF(CNV0_CNV_MODE, CNV_STEREO_TYPE, mask_sh),\
95 SF(CNV0_CNV_MODE, CNV_INTERLACED_MODE, mask_sh),\
96 SF(CNV0_CNV_MODE, CNV_EYE_SELECTION, mask_sh),\
99 SF(CNV0_CNV_MODE, CNV_STEREO_SPLIT, mask_sh),\
100 SF(CNV0_CNV_MODE, CNV_NEW_CONTENT, mask_sh),\
[all …]
A Ddcn10_mpc.h64 SF(MPCC0_MPCC_TOP_SEL, MPCC_TOP_SEL, mask_sh),\
65 SF(MPCC0_MPCC_BOT_SEL, MPCC_BOT_SEL, mask_sh),\
66 SF(MPCC0_MPCC_CONTROL, MPCC_MODE, mask_sh),\
72 SF(MPCC0_MPCC_STATUS, MPCC_IDLE, mask_sh),\
73 SF(MPCC0_MPCC_STATUS, MPCC_BUSY, mask_sh),\
74 SF(MPCC0_MPCC_OPP_ID, MPCC_OPP_ID, mask_sh),\
75 SF(MPCC0_MPCC_BG_G_Y, MPCC_BG_G_Y, mask_sh),\
76 SF(MPCC0_MPCC_BG_R_CR, MPCC_BG_R_CR, mask_sh),\
77 SF(MPCC0_MPCC_BG_B_CB, MPCC_BG_B_CB, mask_sh),\
78 SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_EN, mask_sh),\
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dcn201/
A Ddcn201_optc.h49 SF(OTG0_OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, mask_sh),\
51 SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_START_X, mask_sh),\
52 SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_END_X, mask_sh), \
53 SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_START_Y, mask_sh),\
54 SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_END_Y, mask_sh),\
58 SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_MODE, mask_sh), \
63 SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DSC_MODE, mask_sh),\
65 SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_DSC_SLICE_WIDTH, mask_sh),\
66 SF(DWB_SOURCE_SELECT, OPTC_DWB0_SOURCE_SELECT, mask_sh),\
67 SF(DWB_SOURCE_SELECT, OPTC_DWB1_SOURCE_SELECT, mask_sh),\
[all …]
A Ddcn201_mpc.h44 SF(MPC_OUT0_MUX, MPC_OUT_RATE_CONTROL, mask_sh),\
45 SF(MPC_OUT0_MUX, MPC_OUT_RATE_CONTROL_DISABLE, mask_sh),\
46 SF(MPC_OUT0_MUX, MPC_OUT_FLOW_CONTROL_MODE, mask_sh),\
47 SF(MPC_OUT0_MUX, MPC_OUT_FLOW_CONTROL_COUNT0, mask_sh),\
48 SF(MPC_OUT0_MUX, MPC_OUT_FLOW_CONTROL_COUNT1, mask_sh)
/linux/drivers/gpu/drm/amd/display/dc/dce/
A Ddce_audio.h44 #define SF(reg_name, field_name, post_fix)\ macro
50 SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, mask_sh),\
54 SF(DCCG_AUDIO_DTO0_MODULE, DCCG_AUDIO_DTO0_MODULE, mask_sh),\
55 SF(DCCG_AUDIO_DTO0_PHASE, DCCG_AUDIO_DTO0_PHASE, mask_sh),\
56 SF(DCCG_AUDIO_DTO1_MODULE, DCCG_AUDIO_DTO1_MODULE, mask_sh),\
57 SF(DCCG_AUDIO_DTO1_PHASE, DCCG_AUDIO_DTO1_PHASE, mask_sh),\
70 SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, mask_sh),\
71 SF(DCCG_AUDIO_DTO0_MODULE, DCCG_AUDIO_DTO0_MODULE, mask_sh),\
72 SF(DCCG_AUDIO_DTO0_PHASE, DCCG_AUDIO_DTO0_PHASE, mask_sh),\
73 SF(DCCG_AUDIO_DTO1_MODULE, DCCG_AUDIO_DTO1_MODULE, mask_sh),\
[all …]
A Ddce_mem_input.h246 SF(PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, mask_sh),\
247 SF(PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED, mask_sh)
274 SF(PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, mask_sh),\
275 SF(PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED, mask_sh)
321 SF(DCHUB_FB_LOCATION, FB_TOP, mask_sh),\
322 SF(DCHUB_FB_LOCATION, FB_BASE, mask_sh),\
323 SF(DCHUB_AGP_BASE, AGP_BASE, mask_sh),\
324 SF(DCHUB_AGP_BOT, AGP_BOT, mask_sh),\
325 SF(DCHUB_AGP_TOP, AGP_TOP, mask_sh)
329 SF(DCP0_GRPH_SECONDARY_SURFACE_ADDRESS, GRPH_SECONDARY_DFQ_ENABLE, mask_sh),\
A Ddce_hwseq.h686 SF(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, mask_sh)
728 SF(DCFEV_CLOCK_CONTROL, DCFEV_CLOCK_ENABLE, mask_sh),\
736 SF(DCHUB_FB_LOCATION, FB_TOP, mask_sh),\
737 SF(DCHUB_FB_LOCATION, FB_BASE, mask_sh),\
738 SF(DCHUB_AGP_BASE, AGP_BASE, mask_sh),\
739 SF(DCHUB_AGP_BOT, AGP_BOT, mask_sh),\
740 SF(DCHUB_AGP_TOP, AGP_TOP, mask_sh)
/linux/tools/lib/traceevent/plugins/
A Dplugin_mac80211.c42 #define SF(fn) tep_print_num_field(s, fn ":%d", event, fn, record, 0) macro
58 SF("assoc"); SP(); in drv_bss_info_changed()
59 SF("aid"); SP(); in drv_bss_info_changed()
60 SF("cts"); SP(); in drv_bss_info_changed()
61 SF("shortpre"); SP(); in drv_bss_info_changed()
62 SF("shortslot"); SP(); in drv_bss_info_changed()
63 SF("dtimper"); SP(); in drv_bss_info_changed()
65 SF("bcnint"); SP(); in drv_bss_info_changed()
68 SF("enable_beacon"); in drv_bss_info_changed()
70 SF("ht_operation_mode"); in drv_bss_info_changed()
/linux/fs/reiserfs/
A Dprocfs.c50 #define SF( x ) ( r -> x ) macro
51 #define SFP( x ) SF( s_proc_info_data.x )
102 SF(s_mount_state) == REISERFS_VALID_FS ? in show_super()
118 SF(s_disk_reads), SF(s_disk_writes), SF(s_fix_nodes), in show_super()
119 SF(s_do_balance), SF(s_unneeded_left_neighbor), in show_super()
120 SF(s_good_search_by_key_reada), SF(s_bmaps), in show_super()
121 SF(s_bmaps_without_search), SF(s_direct2indirect), in show_super()
122 SF(s_indirect2direct), SFP(max_hash_collisions), SFP(breads), in show_super()
/linux/Documentation/networking/device_drivers/ethernet/mellanox/
A Dmlx5.rst199 2. VF/SF representor bonding (Usually used for Live migration)
357 device created for the PCI VF/SF.
391 SF state setup
393 To use the SF, the user must active the SF using the SF function state
453 - Show the SF port operational state::
706 SF tracepoints:
708 - mlx5_sf_add: trace addition of the SF port::
715 - mlx5_sf_free: trace freeing of the SF port::
743 - mlx5_sf_vhca_event: trace SF vhca event and state::
750 - mlx5_sf_dev_add : trace SF device add event::
[all …]
/linux/scripts/selinux/
A Dinstall_policy.sh9 SF=`which setfiles`
78 $SF -F file_contexts /
83 $SF -F file_contexts $mounts
/linux/Documentation/devicetree/bindings/rtc/
A Depson,rtc7301.txt1 EPSON TOYOCOM RTC-7301SF/DG
/linux/arch/x86/kernel/
A Duprobes.c594 COND(78, 79, XF(SF)) \
597 COND(7c, 7d, XF(SF) != XF(OF)) \
598 COND(7e, 7f, XF(ZF) || XF(SF) != XF(OF))
/linux/tools/testing/selftests/sgx/
A Dtest_encl_bootstrap.S68 add %rdx, %rdx # OF = SF = AF = CF = 0; ZF = PF = 1
/linux/drivers/gpu/drm/nouveau/dispnv50/
A Dcrc907d.c53 crc_args |= NVDEF(NV907D, HEAD_SET_CRC_CONTROL, PRIMARY_OUTPUT, SF(i)); in crc907d_set_src()

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