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Searched refs:SR (Results 1 – 25 of 144) sorted by relevance

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/linux/drivers/gpu/drm/amd/display/dc/dce/
A Ddce_hwseq.h116 SR(BLNDV_CONTROL),\
158 SR(DCHUB_AGP_BASE),\
159 SR(DCHUB_AGP_BOT),\
160 SR(DCHUB_AGP_TOP)
172 SR(REFCLK_CNTL), \
177 SR(DCFCLK_CNTL),\
178 SR(DCFCLK_CNTL), \
250 SR(MPC_CRC_CTRL), \
393 SR(REFCLK_CNTL), \
398 SR(DCFCLK_CNTL),\
[all …]
A Ddce_dmcu.h33 SR(DMCU_CTRL), \
34 SR(DMCU_STATUS), \
51 SR(DC_DMCU_SCRATCH)
55 SR(DMCU_CTRL), \
56 SR(DMCU_STATUS), \
68 SR(DC_DMCU_SCRATCH)
72 SR(DMCU_CTRL), \
73 SR(DMCU_STATUS), \
86 SR(DC_DMCU_SCRATCH)
94 SR(DMU_MEM_PWR_CNTL)
[all …]
A Ddce_abm.h33 SR(MASTER_COMM_CNTL_REG), \
34 SR(MASTER_COMM_CMD_REG), \
35 SR(MASTER_COMM_DATA_REG1)
39 SR(DC_ABM1_HG_SAMPLE_RATE), \
42 SR(DC_ABM1_HG_MISC_CTRL), \
46 SR(BL1_PWM_USER_LEVEL), \
50 SR(DC_ABM1_ACE_THRES_12), \
51 SR(BIOS_SCRATCH_2)
74 SR(DC_ABM1_HG_MISC_CTRL), \
78 SR(BL1_PWM_USER_LEVEL), \
[all …]
A Ddce_panel_cntl.h39 SR(BL_PWM_CNTL), \
40 SR(BL_PWM_CNTL2), \
41 SR(BL_PWM_PERIOD_CNTL), \
42 SR(BL_PWM_GRP1_REG_LOCK), \
43 SR(BIOS_SCRATCH_2)
53 SR(BL_PWM_CNTL), \
54 SR(BL_PWM_CNTL2), \
55 SR(BL_PWM_PERIOD_CNTL), \
56 SR(BL_PWM_GRP1_REG_LOCK), \
A Ddce_link_encoder.h48 SR(DMCU_RAM_ACCESS_CTRL), \
49 SR(DMCU_IRAM_RD_CTRL), \
50 SR(DMCU_IRAM_RD_DATA), \
51 SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \
77 SR(DCI_MEM_PWR_STATUS)
82 SR(DMCU_RAM_ACCESS_CTRL), \
83 SR(DMCU_IRAM_RD_CTRL), \
84 SR(DMCU_IRAM_RD_DATA), \
115 SR(DCI_MEM_PWR_STATUS)
122 SR(DCI_MEM_PWR_STATUS)
[all …]
A Ddce_audio.h33 SR(AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS),\
34 SR(AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES),\
35 SR(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES),\
36 SR(DCCG_AUDIO_DTO_SOURCE),\
37 SR(DCCG_AUDIO_DTO0_MODULE),\
38 SR(DCCG_AUDIO_DTO0_PHASE),\
39 SR(DCCG_AUDIO_DTO1_MODULE),\
40 SR(DCCG_AUDIO_DTO1_PHASE)
A Ddce_i2c_hw.h88 SR(DC_I2C_ARBITRATION),\
89 SR(DC_I2C_CONTROL),\
90 SR(DC_I2C_SW_STATUS),\
91 SR(DC_I2C_TRANSACTION0),\
92 SR(DC_I2C_TRANSACTION1),\
93 SR(DC_I2C_TRANSACTION2),\
94 SR(DC_I2C_TRANSACTION3),\
95 SR(DC_I2C_DATA),\
96 SR(MICROSECOND_TIME_BASE_DIV)
100 SR(DIO_MEM_PWR_CTRL),\
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dcn30/
A Ddcn30_dwb.h48 SR(FC_MODE_CTRL),\
49 SR(FC_FLOW_CTRL),\
50 SR(FC_WINDOW_START),\
51 SR(FC_WINDOW_SIZE),\
52 SR(FC_SOURCE_SIZE),\
53 SR(DWB_UPDATE_CTRL),\
54 SR(DWB_CRC_CTRL),\
57 SR(DWB_CRC_VAL_R_G),\
58 SR(DWB_CRC_VAL_B_A),\
59 SR(DWB_OUT_CTRL),\
[all …]
A Ddcn30_hubbub.h40 SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A),\
41 SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B),\
42 SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C),\
43 SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D),\
44 SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A),\
45 SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B),\
46 SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C),\
47 SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D),\
48 SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A),\
49 SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B),\
[all …]
A Ddcn30_dccg.h34 SR(PHYASYMCLK_CLOCK_CNTL),\
35 SR(PHYBSYMCLK_CLOCK_CNTL),\
36 SR(PHYCSYMCLK_CLOCK_CNTL)
45 SR(PHYASYMCLK_CLOCK_CNTL),\
46 SR(PHYBSYMCLK_CLOCK_CNTL),\
47 SR(PHYCSYMCLK_CLOCK_CNTL)
/linux/drivers/gpu/drm/amd/display/dc/dcn10/
A Ddcn10_hubbub.h46 SR(DCHUBBUB_ARB_SAT_LEVEL),\
48 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
49 SR(DCHUBBUB_TEST_DEBUG_INDEX), \
50 SR(DCHUBBUB_TEST_DEBUG_DATA),\
51 SR(DCHUBBUB_SOFT_RESET)
73 SR(DCHUBBUB_SDPIF_FB_TOP),\
74 SR(DCHUBBUB_SDPIF_FB_BASE),\
75 SR(DCHUBBUB_SDPIF_FB_OFFSET),\
76 SR(DCHUBBUB_SDPIF_AGP_BASE),\
77 SR(DCHUBBUB_SDPIF_AGP_BOT),\
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dcn31/
A Ddcn31_hubbub.h33 SR(DCHVM_CTRL0),\
34 SR(DCHVM_MEM_CTRL),\
35 SR(DCHVM_CLK_CTRL),\
36 SR(DCHVM_RIOMMU_CTRL0),\
37 SR(DCHVM_RIOMMU_STAT0),\
38 SR(DCHUBBUB_DET0_CTRL),\
39 SR(DCHUBBUB_DET1_CTRL),\
40 SR(DCHUBBUB_DET2_CTRL),\
41 SR(DCHUBBUB_DET3_CTRL),\
42 SR(DCHUBBUB_COMPBUF_CTRL),\
[all …]
A Ddcn31_dccg.h36 SR(DPPCLK_DTO_CTRL),\
41 SR(PHYASYMCLK_CLOCK_CNTL),\
42 SR(PHYBSYMCLK_CLOCK_CNTL),\
46 SR(DPSTREAMCLK_CNTL),\
47 SR(SYMCLK32_SE_CNTL),\
48 SR(SYMCLK32_LE_CNTL),\
64 SR(DENTIST_DISPCLK_CNTL),\
65 SR(DSCCLK0_DTO_PARAM),\
66 SR(DSCCLK1_DTO_PARAM),\
67 SR(DSCCLK2_DTO_PARAM),\
[all …]
A Ddcn31_resource.c271 #define SR(reg_name)\ macro
820 SR(DIO_MEM_PWR_CTRL), \
826 SR(DCFCLK_CNTL),\
845 SR(MPC_CRC_CTRL), \
863 SR(D1VGA_CONTROL), \
864 SR(D2VGA_CONTROL), \
865 SR(D3VGA_CONTROL), \
866 SR(D4VGA_CONTROL), \
867 SR(D5VGA_CONTROL), \
868 SR(D6VGA_CONTROL), \
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dcn21/
A Ddcn21_hubbub.h31 SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A),\
32 SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B),\
33 SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C),\
34 SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D),\
35 SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A),\
43 SR(DCHUBBUB_ARB_HOSTVM_CNTL), \
44 SR(DCHVM_CTRL0), \
45 SR(DCHVM_MEM_CTRL), \
46 SR(DCHVM_CLK_CTRL), \
47 SR(DCHVM_RIOMMU_CTRL0), \
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dcn20/
A Ddcn20_hubbub.h37 SR(DCHUBBUB_CRC_CTRL), \
38 SR(DCN_VM_FB_LOCATION_BASE),\
39 SR(DCN_VM_FB_LOCATION_TOP),\
40 SR(DCN_VM_FB_OFFSET),\
41 SR(DCN_VM_AGP_BOT),\
42 SR(DCN_VM_AGP_TOP),\
43 SR(DCN_VM_AGP_BASE),\
44 SR(DCN_VM_FAULT_ADDR_MSB), \
45 SR(DCN_VM_FAULT_ADDR_LSB), \
46 SR(DCN_VM_FAULT_CNTL), \
[all …]
/linux/Documentation/networking/
A Dseg6-sysctl.rst12 Accept or drop SR-enabled IPv6 packets on this interface.
20 Define HMAC policy for ingress SR-enabled packets on this interface.
23 * 0 - Accept SR packets without HMAC, validate SR packets with HMAC
24 * 1 - Drop SR packets without HMAC, validate SR packets with HMAC
30 IPv6 header in case of SR T.encaps
/linux/Documentation/PCI/
A Dpci-iov-howto.rst15 What is SR-IOV
18 Single Root I/O Virtualization (SR-IOV) is a PCI Express Extended
34 How can I enable SR-IOV capability
37 Multiple methods are available for SR-IOV enablement.
40 If the hardware has SR-IOV capability, loading its PF driver would
63 SR-IOV API
66 To enable SR-IOV capability:
79 To disable SR-IOV capability:
91 command below before enabling SR-IOV capabilities. This is the
99 command below before enabling SR-IOV capabilities. Updating this
[all …]
/linux/drivers/macintosh/
A Dvia-cuda.c346 (void)in_8(&via[SR]); in sync_egret()
361 (void)in_8(&via[SR]); in sync_egret()
398 (void)in_8(&via[SR]); in cuda_init_via()
409 (void)in_8(&via[SR]); in cuda_init_via()
418 (void)in_8(&via[SR]); in cuda_init_via()
599 (void)in_8(&via[SR]); in cuda_interrupt()
609 (void)in_8(&via[SR]); in cuda_interrupt()
620 (void)in_8(&via[SR]); in cuda_interrupt()
639 (void)in_8(&via[SR]); in cuda_interrupt()
663 (void)in_8(&via[SR]); in cuda_interrupt()
[all …]
A Dvia-macii.c51 #define SR (10*RS) /* Shift register */ macro
178 x = via[SR]; in macii_init_via()
341 via[SR] = req->data[1]; in macii_start()
400 x = via[SR]; in macii_interrupt()
450 x = via[SR]; in macii_interrupt()
463 x = via[SR]; in macii_interrupt()
473 x = via[SR]; in macii_interrupt()
489 via[SR] = req->data[data_index++]; in macii_interrupt()
502 x = via[SR]; in macii_interrupt()
557 x = via[SR]; in macii_interrupt()
/linux/arch/alpha/math-emu/
A Dmath.c106 FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SR); in alpha_fp_emul()
140 FP_SUB_S(SR, SA, SB); in alpha_fp_emul()
144 FP_ADD_S(SR, SA, SB); in alpha_fp_emul()
148 FP_MUL_S(SR, SA, SB); in alpha_fp_emul()
152 FP_DIV_S(SR, SA, SB); in alpha_fp_emul()
156 FP_SQRT_S(SR, SB); in alpha_fp_emul()
226 FP_CONV(S,D,1,1,SR,DB); in alpha_fp_emul()
264 FP_FROM_INT_S(SR, ((long)vb), 64, long); in alpha_fp_emul()
276 FP_PACK_SP(&vc, SR); in alpha_fp_emul()
/linux/arch/sparc/math-emu/
A Dmath_32.c286 FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SR); in do_one_mathemu()
428 case FADDS: FP_ADD_S (SR, SA, SB); break; in do_one_mathemu()
432 case FSUBS: FP_SUB_S (SR, SA, SB); break; in do_one_mathemu()
436 case FMULS: FP_MUL_S (SR, SA, SB); break; in do_one_mathemu()
444 case FDIVS: FP_DIV_S (SR, SA, SB); break; in do_one_mathemu()
448 case FSQRTS: FP_SQRT_S (SR, SB); break; in do_one_mathemu()
460 case FITOS: IR = rs2->s; FP_FROM_INT_S (SR, IR, 32, int); break; in do_one_mathemu()
467 case FDTOS: FP_CONV (S, D, 1, 2, SR, DB); break; in do_one_mathemu()
468 case FQTOS: FP_CONV (S, Q, 1, 4, SR, QB); break; in do_one_mathemu()
507 case 5: FP_PACK_SP (rd, SR); break; in do_one_mathemu()
A Dmath_64.c181 FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SR); in do_mathemu()
433 case FADDS: FP_ADD_S (SR, SA, SB); break; in do_mathemu()
437 case FSUBS: FP_SUB_S (SR, SA, SB); break; in do_mathemu()
441 case FMULS: FP_MUL_S (SR, SA, SB); break; in do_mathemu()
449 case FDIVS: FP_DIV_S (SR, SA, SB); break; in do_mathemu()
453 case FSQRTS: FP_SQRT_S (SR, SB); break; in do_mathemu()
471 case FXTOS: XR = rs2->d; FP_FROM_INT_S (SR, XR, 64, long); break; in do_mathemu()
474 case FITOS: IR = rs2->s; FP_FROM_INT_S (SR, IR, 32, int); break; in do_mathemu()
481 case FDTOS: FP_CONV (S, D, 1, 1, SR, DB); break; in do_mathemu()
482 case FQTOS: FP_CONV (S, Q, 1, 2, SR, QB); break; in do_mathemu()
[all …]
/linux/Documentation/sh/
A Dregister-banks.rst11 bank (selected by SR.RB, only r0 ... r7 are banked), whereas other families
14 SR.RB banking
18 r0 ... r7 if SR.RB is set to the bank we are interested in, otherwise ldc/stc
20 when in the context of another bank. The developer must keep the SR.RB value
37 - The SR.IMASK interrupt handler makes use of this to set the
/linux/drivers/video/fbdev/omap2/omapfb/dss/
A Ddispc.c282 #define SR(reg) \ macro
293 SR(IRQENABLE); in dispc_save_context()
294 SR(CONTROL); in dispc_save_context()
295 SR(CONFIG); in dispc_save_context()
296 SR(LINE_NUMBER); in dispc_save_context()
301 SR(CONTROL2); in dispc_save_context()
302 SR(CONFIG2); in dispc_save_context()
305 SR(CONTROL3); in dispc_save_context()
306 SR(CONFIG3); in dispc_save_context()
387 SR(DIVISOR); in dispc_save_context()
[all …]

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