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Searched refs:UPLL_RESET_MASK (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/gpu/drm/radeon/
A Drv770.c87 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~(UPLL_RESET_MASK | UPLL_SLEEP_MASK)); in rv770_set_uvd_clocks()
98 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK); in rv770_set_uvd_clocks()
116 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); in rv770_set_uvd_clocks()
A Drv770d.h43 # define UPLL_RESET_MASK 0x00000001 macro
A Dr600.c215 UPLL_RESET_MASK | UPLL_SLEEP_MASK | UPLL_CTLREQ_MASK)); in r600_set_uvd_clocks()
248 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK); in r600_set_uvd_clocks()
272 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); in r600_set_uvd_clocks()
A Devergreen.c1221 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); in evergreen_set_uvd_clocks()
1230 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK); in evergreen_set_uvd_clocks()
1255 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); in evergreen_set_uvd_clocks()
A Dsid.h128 # define UPLL_RESET_MASK 0x00000001 macro
A Dsi.c7024 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); in si_set_uvd_clocks()
7033 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK); in si_set_uvd_clocks()
7058 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); in si_set_uvd_clocks()
A Devergreend.h349 # define UPLL_RESET_MASK 0x00000001 macro
A Dr600d.h1557 # define UPLL_RESET_MASK 0x00000001 macro
/linux/drivers/gpu/drm/amd/amdgpu/
A Dsi.c1809 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); in si_set_uvd_clocks()
1818 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK); in si_set_uvd_clocks()
1845 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); in si_set_uvd_clocks()
A Dsid.h129 # define UPLL_RESET_MASK 0x00000001 macro

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