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Searched refs:VC4_SET_FIELD (Results 1 – 13 of 13) sorted by relevance

/linux/drivers/gpu/drm/vc4/
A Dvc4_hdmi_phy.c384 VC4_SET_FIELD(phy_get_rm_offset(vco_freq), in vc5_hdmi_phy_init()
410 VC4_SET_FIELD(2, VC4_HDMI_RM_FORMAT_SHIFT)); in vc5_hdmi_phy_init()
423 VC4_SET_FIELD(phy_get_cp_current(vco_freq), in vc5_hdmi_phy_init()
425 VC4_SET_FIELD(1, VC4_HDMI_TX_PHY_CTL_3_CP) | in vc5_hdmi_phy_init()
427 VC4_SET_FIELD(3, VC4_HDMI_TX_PHY_CTL_3_CZ) | in vc5_hdmi_phy_init()
428 VC4_SET_FIELD(4, VC4_HDMI_TX_PHY_CTL_3_RP) | in vc5_hdmi_phy_init()
464 VC4_SET_FIELD(chan0_settings->res_sel_data, in vc5_hdmi_phy_init()
466 VC4_SET_FIELD(chan1_settings->res_sel_data, in vc5_hdmi_phy_init()
468 VC4_SET_FIELD(chan2_settings->res_sel_data, in vc5_hdmi_phy_init()
470 VC4_SET_FIELD(clock_settings->res_sel_data, in vc5_hdmi_phy_init()
[all …]
A Dvc4_dsi.c887 VC4_SET_FIELD(7, DSI_PHY_AFEC0_CTATADJ)); in vc4_dsi_encoder_enable()
903 VC4_SET_FIELD(7, DSI_PHY_AFEC0_CTATADJ) | in vc4_dsi_encoder_enable()
969 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 0, 8), in vc4_dsi_encoder_enable()
998 VC4_SET_FIELD(0, DSI_HS_DLT4_ANLAT)); in vc4_dsi_encoder_enable()
1015 VC4_SET_FIELD(lpx, DSI_HS_DLT6_TA_SURE) | in vc4_dsi_encoder_enable()
1017 VC4_SET_FIELD(lpx, DSI_HS_DLT6_LP_LPX)); in vc4_dsi_encoder_enable()
1020 VC4_SET_FIELD(dsi_esc_timing(1000000), in vc4_dsi_encoder_enable()
1079 VC4_SET_FIELD(dsi->divider, in vc4_dsi_encoder_enable()
1117 pkth |= VC4_SET_FIELD(packet.header[1] | in vc4_dsi_host_transfer()
1146 pktc |= VC4_SET_FIELD(DSI_TXPKT1C_CMD_CTRL_RX, in vc4_dsi_host_transfer()
[all …]
A Dvc4_plane.c854 VC4_SET_FIELD(vc4_state->crtc_w, in vc4_plane_mode_set()
856 VC4_SET_FIELD(vc4_state->crtc_h, in vc4_plane_mode_set()
870 VC4_SET_FIELD(vc4_state->src_w[0], in vc4_plane_mode_set()
872 VC4_SET_FIELD(vc4_state->src_h[0], in vc4_plane_mode_set()
902 VC4_SET_FIELD(vc4_state->crtc_x, in vc4_plane_mode_set()
906 VC4_SET_FIELD(vc4_state->crtc_y, in vc4_plane_mode_set()
912 VC4_SET_FIELD(state->alpha >> 4, in vc4_plane_mode_set()
927 VC4_SET_FIELD(vc4_state->crtc_w, in vc4_plane_mode_set()
929 VC4_SET_FIELD(vc4_state->crtc_h, in vc4_plane_mode_set()
936 VC4_SET_FIELD(vc4_state->src_w[0], in vc4_plane_mode_set()
[all …]
A Dvc4_kms.c163 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[0]), in vc4_ctm_commit()
165 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[3]), in vc4_ctm_commit()
167 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[6]), in vc4_ctm_commit()
170 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[1]), in vc4_ctm_commit()
172 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[4]), in vc4_ctm_commit()
257 dsp3_mux = VC4_SET_FIELD(3, SCALER_DISPCTRL_DSP3_MUX); in vc4_hvs_pv_muxing_commit()
259 dsp3_mux = VC4_SET_FIELD(2, SCALER_DISPCTRL_DSP3_MUX); in vc4_hvs_pv_muxing_commit()
289 VC4_SET_FIELD(mux, SCALER_DISPECTRL_DSP2_MUX)); in vc5_hvs_pv_muxing_commit()
301 VC4_SET_FIELD(mux, SCALER_DISPCTRL_DSP3_MUX)); in vc5_hvs_pv_muxing_commit()
313 VC4_SET_FIELD(mux, SCALER_DISPEOLN_DSP4_MUX)); in vc5_hvs_pv_muxing_commit()
[all …]
A Dvc4_hdmi.c733 VC4_SET_FIELD(mode->crtc_vtotal - in vc4_hdmi_set_timings()
745 VC4_SET_FIELD((mode->htotal - in vc4_hdmi_set_timings()
748 VC4_SET_FIELD((mode->hsync_end - in vc4_hdmi_set_timings()
751 VC4_SET_FIELD((mode->hsync_start - in vc4_hdmi_set_timings()
779 VC4_SET_FIELD(mode->crtc_vtotal - in vc5_hdmi_set_timings()
793 VC4_SET_FIELD((mode->hsync_start - in vc5_hdmi_set_timings()
798 VC4_SET_FIELD((mode->htotal - in vc5_hdmi_set_timings()
801 VC4_SET_FIELD((mode->hsync_end - in vc5_hdmi_set_timings()
1193 VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) | in vc4_hdmi_audio_set_mai_clock()
1360 VC4_SET_FIELD(mai_sample_rate, in vc4_hdmi_audio_prepare()
[all …]
A Dvc4_crtc.c268 ret |= VC4_SET_FIELD((level >> 6), in vc4_crtc_get_fifo_full_level_bits()
271 return ret | VC4_SET_FIELD(level & 0x3f, in vc4_crtc_get_fifo_full_level_bits()
353 VC4_SET_FIELD(mode->hdisplay * pixel_rep / ppc, in vc4_crtc_config_pv()
368 VC4_SET_FIELD(mode->crtc_vtotal - in vc4_crtc_config_pv()
371 VC4_SET_FIELD(mode->crtc_vsync_end - in vc4_crtc_config_pv()
375 VC4_SET_FIELD(mode->crtc_vsync_start - in vc4_crtc_config_pv()
389 VC4_SET_FIELD(mode->htotal * pixel_rep / 2, in vc4_crtc_config_pv()
403 VC4_SET_FIELD(PV_MUX_CFG_RGB_PIXEL_MUX_MODE_NO_SWAP, in vc4_crtc_config_pv()
408 VC4_SET_FIELD(format, PV_CONTROL_FORMAT) | in vc4_crtc_config_pv()
409 VC4_SET_FIELD(pixel_rep - 1, PV_CONTROL_PIXEL_REP) | in vc4_crtc_config_pv()
[all …]
A Dvc4_dpi.c156 dpi_c |= VC4_SET_FIELD(DPI_FORMAT_24BIT_888_RGB, in vc4_dpi_encoder_enable()
160 dpi_c |= VC4_SET_FIELD(DPI_FORMAT_24BIT_888_RGB, in vc4_dpi_encoder_enable()
162 dpi_c |= VC4_SET_FIELD(DPI_ORDER_BGR, DPI_ORDER); in vc4_dpi_encoder_enable()
165 dpi_c |= VC4_SET_FIELD(DPI_FORMAT_18BIT_666_RGB_2, in vc4_dpi_encoder_enable()
169 dpi_c |= VC4_SET_FIELD(DPI_FORMAT_18BIT_666_RGB_1, in vc4_dpi_encoder_enable()
173 dpi_c |= VC4_SET_FIELD(DPI_FORMAT_16BIT_565_RGB_3, in vc4_dpi_encoder_enable()
182 dpi_c |= VC4_SET_FIELD(DPI_FORMAT_24BIT_888_RGB, DPI_FORMAT); in vc4_dpi_encoder_enable()
A Dvc4_txp.c302 VC4_SET_FIELD(0xf, TXP_BYTE_ENABLE) | in vc4_txp_connector_atomic_commit()
303 VC4_SET_FIELD(txp_fmts[i], TXP_FORMAT); in vc4_txp_connector_atomic_commit()
312 VC4_SET_FIELD(mode->hdisplay, TXP_WIDTH) | in vc4_txp_connector_atomic_commit()
313 VC4_SET_FIELD(mode->vdisplay, TXP_HEIGHT)); in vc4_txp_connector_atomic_commit()
A Dvc4_hvs.c274 dispctrl |= VC4_SET_FIELD(mode->hdisplay, in vc4_hvs_init_channel()
276 VC4_SET_FIELD(mode->vdisplay, in vc4_hvs_init_channel()
280 dispctrl |= VC4_SET_FIELD(mode->hdisplay, in vc4_hvs_init_channel()
282 VC4_SET_FIELD(mode->vdisplay, in vc4_hvs_init_channel()
666 dispctrl |= VC4_SET_FIELD(2, SCALER_DISPCTRL_DSP3_MUX); in vc4_hvs_bind()
A Dvc4_gem.c441 VC4_SET_FIELD(0xf, V3D_SLCACTL_T1CC) | in vc4_flush_caches()
442 VC4_SET_FIELD(0xf, V3D_SLCACTL_T0CC) | in vc4_flush_caches()
443 VC4_SET_FIELD(0xf, V3D_SLCACTL_UCC) | in vc4_flush_caches()
444 VC4_SET_FIELD(0xf, V3D_SLCACTL_ICC)); in vc4_flush_caches()
456 VC4_SET_FIELD(0xf, V3D_SLCACTL_T1CC) | in vc4_flush_texture_caches()
457 VC4_SET_FIELD(0xf, V3D_SLCACTL_T0CC)); in vc4_flush_texture_caches()
A Dvc4_validate.c409 VC4_SET_FIELD(VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_32, in validate_tile_binning_config()
411 VC4_SET_FIELD(VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_128, in validate_tile_binning_config()
A Dvc4_render_cl.c84 VC4_SET_FIELD(VC4_LOADSTORE_TILE_BUFFER_NONE, in vc4_store_before_load()
A Dvc4_regs.h14 #define VC4_SET_FIELD(value, field) \ macro

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