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Searched refs:WM_A (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/
A Ddcn30_clk_mgr.c116 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].valid = true; in dcn3_build_wm_range_table()
117 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us = pstate_latency_us; in dcn3_build_wm_range_table()
118 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us = sr_exit_time_us; in dcn3_build_wm_range_table()
119 …clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us = sr_enter… in dcn3_build_wm_range_table()
120 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE; in dcn3_build_wm_range_table()
121 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = 0; in dcn3_build_wm_range_table()
122 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_dcfclk = 0xFFFF; in dcn3_build_wm_range_table()
123 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_uclk = min_uclk_mhz; in dcn3_build_wm_range_table()
124 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_uclk = 0xFFFF; in dcn3_build_wm_range_table()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/
A Drn_clk_mgr.c516 ranges->writer_wm_sets[0].wm_inst = WM_A; in build_watermark_ranges()
629 .wm_inst = WM_A,
666 .wm_inst = WM_A,
703 .wm_inst = WM_A,
740 .wm_inst = WM_A,
777 .wm_inst = WM_A,
814 .wm_inst = WM_A,
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
A Ddcn31_clk_mgr.c335 .wm_inst = WM_A,
372 .wm_inst = WM_A,
458 table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A; in dcn31_build_watermark_ranges()
/linux/drivers/gpu/drm/amd/display/dc/inc/hw/
A Dclk_mgr.h37 #define WM_A 0 macro
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
A Dvg_clk_mgr.c446 table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A; in vg_build_watermark_ranges()
545 .wm_inst = WM_A,
582 .wm_inst = WM_A,
/linux/drivers/gpu/drm/amd/display/dc/calcs/
A Ddcn_calcs.c43 #define WM_A 0 macro
1577 ranges.reader_wm_sets[0].wm_inst = WM_A; in dcn_bw_notify_pplib_of_wm_ranges()
1582 ranges.writer_wm_sets[0].wm_inst = WM_A; in dcn_bw_notify_pplib_of_wm_ranges()
1589 ranges.reader_wm_sets[0].wm_inst = WM_A; in dcn_bw_notify_pplib_of_wm_ranges()
1594 ranges.writer_wm_sets[0].wm_inst = WM_A; in dcn_bw_notify_pplib_of_wm_ranges()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn301/
A Ddcn301_fpu.c366 table_entry = &bw_params->wm_table.entries[WM_A]; in dcn301_calculate_wm_and_dlg()
/linux/drivers/gpu/drm/amd/display/dc/dcn30/
A Ddcn30_resource.c2273 dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us; in dcn30_calculate_wm_and_dlg_fp()
2278 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].valid) { in dcn30_update_soc_for_wm_a()
2279 …ram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_l… in dcn30_update_soc_for_wm_a()
2280 ….sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter… in dcn30_update_soc_for_wm_a()
2281 …context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_in… in dcn30_update_soc_for_wm_a()
/linux/drivers/gpu/drm/amd/display/dc/dcn31/
A Ddcn31_resource.c1847 if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) { in dcn31_update_soc_for_wm_a()
1848 …oc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].pstate_latency_us; in dcn31_update_soc_for_wm_a()
1849 …soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_enter_plus_exit… in dcn31_update_soc_for_wm_a()
1850 …context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_t… in dcn31_update_soc_for_wm_a()
/linux/drivers/gpu/drm/amd/display/dc/dcn21/
A Ddcn21_resource.c1175 table_entry = &bw_params->wm_table.entries[WM_A]; in dcn21_calculate_wm()

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