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Searched refs:WREG32 (Results 1 – 25 of 154) sorted by relevance

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/linux/drivers/misc/habanalabs/goya/
A Dgoya_security.c23 WREG32(pb_addr, 0); in goya_pb_set_block()
81 WREG32(pb_addr + word_offset, ~mask); in goya_init_mme_protection_bits()
104 WREG32(pb_addr + word_offset, ~mask); in goya_init_mme_protection_bits()
128 WREG32(pb_addr + word_offset, ~mask); in goya_init_mme_protection_bits()
160 WREG32(pb_addr + word_offset, ~mask); in goya_init_mme_protection_bits()
180 WREG32(pb_addr + word_offset, ~mask); in goya_init_mme_protection_bits()
194 WREG32(pb_addr + word_offset, ~mask); in goya_init_mme_protection_bits()
210 WREG32(pb_addr + word_offset, ~mask); in goya_init_mme_protection_bits()
228 WREG32(pb_addr + word_offset, ~mask); in goya_init_mme_protection_bits()
251 WREG32(pb_addr + word_offset, ~mask); in goya_init_mme_protection_bits()
[all …]
A Dgoya_coresight.c340 WREG32(base_reg + 0x20, 0); in goya_config_etf()
352 WREG32(base_reg + 0x20, 1); in goya_config_etf()
354 WREG32(base_reg + 0x34, 0); in goya_config_etf()
355 WREG32(base_reg + 0x28, 0); in goya_config_etf()
414 WREG32(mmPSOC_ETR_CTL, 0); in goya_config_etr()
446 WREG32(mmPSOC_ETR_DBALO, in goya_config_etr()
448 WREG32(mmPSOC_ETR_DBAHI, in goya_config_etr()
450 WREG32(mmPSOC_ETR_FFCR, 3); in goya_config_etr()
452 WREG32(mmPSOC_ETR_CTL, 1); in goya_config_etr()
458 WREG32(mmPSOC_ETR_PSCR, 0); in goya_config_etr()
[all …]
A Dgoya.c1280 WREG32(mmCPU_CQ_BASE_ADDR_LOW, in goya_init_cpu_queues()
1290 WREG32(mmCPU_EQ_CI, 0); in goya_init_cpu_queues()
1292 WREG32(mmCPU_IF_PF_PQ_PI, 0); in goya_init_cpu_queues()
1523 WREG32(mmMME_AGU, 0x0f0f0f10); in goya_init_golden_registers()
1524 WREG32(mmMME_SEI_MASK, ~0x0); in goya_init_golden_registers()
1778 WREG32(mmMME_QM_PQ_PI, 0); in goya_init_mme_qman()
1779 WREG32(mmMME_QM_PQ_CI, 0); in goya_init_mme_qman()
1997 WREG32(mmMME_QM_GLBL_CFG0, 0); in goya_disable_internal_queues()
2624 WREG32(mmMMU_MMU_ENABLE, 1); in goya_mmu_init()
2625 WREG32(mmMMU_SPI_MASK, 0xF); in goya_mmu_init()
[all …]
/linux/drivers/gpu/drm/radeon/
A Drv515.c204 WREG32(MC_IND_INDEX, 0); in rv515_mc_rreg()
216 WREG32(MC_IND_DATA, (v)); in rv515_mc_wreg()
217 WREG32(MC_IND_INDEX, 0); in rv515_mc_wreg()
692 WREG32(index_reg, 0x0); in atom_rv515_force_tv_scaler()
694 WREG32(index_reg, 0x1); in atom_rv515_force_tv_scaler()
696 WREG32(index_reg, 0x2); in atom_rv515_force_tv_scaler()
698 WREG32(index_reg, 0x100); in atom_rv515_force_tv_scaler()
700 WREG32(index_reg, 0x101); in atom_rv515_force_tv_scaler()
702 WREG32(index_reg, 0x102); in atom_rv515_force_tv_scaler()
704 WREG32(index_reg, 0x200); in atom_rv515_force_tv_scaler()
[all …]
A Dradeon_bios.c278 WREG32(AVIVO_D1VGA_CONTROL, in ni_read_disabled_bios()
281 WREG32(AVIVO_D2VGA_CONTROL, in ni_read_disabled_bios()
326 WREG32(AVIVO_D1VGA_CONTROL, in r700_read_disabled_bios()
329 WREG32(AVIVO_D2VGA_CONTROL, in r700_read_disabled_bios()
405 WREG32(AVIVO_D1VGA_CONTROL, in r600_read_disabled_bios()
408 WREG32(AVIVO_D2VGA_CONTROL, in r600_read_disabled_bios()
414 WREG32(R600_ROM_CNTL, in r600_read_disabled_bios()
471 WREG32(RADEON_SEPROM_CNTL1, in avivo_read_disabled_bios()
485 WREG32(AVIVO_D1VGA_CONTROL, in avivo_read_disabled_bios()
488 WREG32(AVIVO_D2VGA_CONTROL, in avivo_read_disabled_bios()
[all …]
A Drv770.c920 WREG32(VM_L2_CNTL2, 0); in rv770_pcie_gart_enable()
966 WREG32(VM_L2_CNTL2, 0); in rv770_pcie_gart_disable()
997 WREG32(VM_L2_CNTL2, 0); in rv770_agp_enable()
1095 WREG32(SCRATCH_UMSK, 0); in r700_cp_stop()
1108 WREG32(CP_RB_CNTL, in rv770_cp_load_microcode()
1575 WREG32(VGT_GS_PER_VS, 2); in rv770_gpu_init()
1580 WREG32(VGT_STRMOUT_EN, 0); in rv770_gpu_init()
1581 WREG32(SX_MISC, 0); in rv770_gpu_init()
1587 WREG32(SPI_INPUT_Z, 0); in rv770_gpu_init()
1601 WREG32(TCP_CNTL, 0); in rv770_gpu_init()
[all …]
A Dvce_v2_0.c46 WREG32(VCE_CLOCK_GATING_B, tmp); in vce_v2_0_set_sw_cg()
56 WREG32(VCE_CGTT_CLK_OVERRIDE, 0); in vce_v2_0_set_sw_cg()
61 WREG32(VCE_CLOCK_GATING_B, tmp); in vce_v2_0_set_sw_cg()
86 WREG32(VCE_CLOCK_GATING_B, tmp); in vce_v2_0_set_dyn_cg()
105 WREG32(VCE_CGTT_CLK_OVERRIDE, 7); in vce_v2_0_disable_cg()
139 WREG32(VCE_CLOCK_GATING_A, tmp); in vce_v2_0_init_cg()
149 WREG32(VCE_CLOCK_GATING_B, tmp); in vce_v2_0_init_cg()
166 WREG32(VCE_CLOCK_GATING_B, 0xf7); in vce_v2_0_resume()
170 WREG32(VCE_LMI_SWAP_CNTL, 0); in vce_v2_0_resume()
171 WREG32(VCE_LMI_SWAP_CNTL1, 0); in vce_v2_0_resume()
[all …]
A Duvd_v1_0.c217 WREG32(MC_CONFIG, 0); in uvd_v1_0_init()
218 WREG32(MC_CONFIG, 1 << 4); in uvd_v1_0_init()
220 WREG32(MC_CONFIG, 0x1f); in uvd_v1_0_init()
274 WREG32(UVD_CGC_GATE, 0); in uvd_v1_0_start()
307 WREG32(UVD_MPC_SET_MUXA1, 0x0); in uvd_v1_0_start()
309 WREG32(UVD_MPC_SET_MUXB1, 0x0); in uvd_v1_0_start()
310 WREG32(UVD_MPC_SET_ALU, 0); in uvd_v1_0_start()
311 WREG32(UVD_MPC_SET_MUX, 0x88); in uvd_v1_0_start()
326 WREG32(UVD_SOFT_RESET, 0); in uvd_v1_0_start()
368 WREG32(UVD_RBC_RB_RPTR, 0x0); in uvd_v1_0_start()
[all …]
A Dr600.c1089 WREG32(HDP_DEBUG1, 0); in r600_pcie_gart_tlb_flush()
1704 WREG32(RLC_CNTL, 0); in r600_gpu_soft_reset()
1836 WREG32(RLC_CNTL, 0); in r600_gpu_pci_config_reset()
1859 WREG32(BUS_CNTL, tmp); in r600_gpu_pci_config_reset()
2173 WREG32(DB_DEBUG, 0); in r600_gpu_init()
2338 WREG32(SX_MISC, 0); in r600_gpu_init()
2375 WREG32(TC_CNTL, tmp); in r600_gpu_init()
2382 WREG32(ARB_POP, tmp); in r600_gpu_init()
2388 WREG32(VC_ENHANCE, 0); in r600_gpu_init()
2654 WREG32(CP_RB_CNTL, in r600_cp_load_microcode()
[all …]
A Dvce_v1_0.c98 WREG32(VCE_RB_WPTR, ring->wptr); in vce_v1_0_set_wptr()
110 WREG32(VCE_CLOCK_GATING_A, tmp); in vce_v1_0_enable_mgcg()
123 WREG32(VCE_CLOCK_GATING_A, tmp); in vce_v1_0_enable_mgcg()
142 WREG32(VCE_CLOCK_GATING_A, tmp); in vce_v1_0_init_cg()
147 WREG32(VCE_CLOCK_GATING_B, tmp); in vce_v1_0_init_cg()
225 WREG32(VCE_CLOCK_GATING_B, 0); in vce_v1_0_resume()
231 WREG32(VCE_LMI_SWAP_CNTL, 0); in vce_v1_0_resume()
232 WREG32(VCE_LMI_SWAP_CNTL1, 0); in vce_v1_0_resume()
233 WREG32(VCE_LMI_VM_CTRL, 0); in vce_v1_0_resume()
298 WREG32(VCE_RB_RPTR, ring->wptr); in vce_v1_0_start()
[all …]
A Dradeon_i2c.c131 WREG32(rec->a_clk_reg, temp); in pre_xfer()
134 WREG32(rec->a_data_reg, temp); in pre_xfer()
138 WREG32(rec->en_clk_reg, temp); in pre_xfer()
213 WREG32(rec->en_clk_reg, val); in set_clock()
466 WREG32(i2c_data, 0); in r100_hw_i2c_xfer()
471 WREG32(i2c_cntl_0, reg); in r100_hw_i2c_xfer()
531 WREG32(i2c_cntl_0, reg); in r100_hw_i2c_xfer()
552 WREG32(i2c_cntl_0, 0); in r100_hw_i2c_xfer()
553 WREG32(i2c_cntl_1, 0); in r100_hw_i2c_xfer()
606 WREG32(rec->a_clk_reg, tmp); in r500_hw_i2c_xfer()
[all …]
A Dni.c65 WREG32(TN_SMC_IND_DATA_0, (v)); in tn_smc_wreg()
1001 WREG32(SRBM_INT_CNTL, 0x1); in cayman_gpu_init()
1002 WREG32(SRBM_INT_ACK, 0x1); in cayman_gpu_init()
1194 WREG32(CP_PERFMON_CNTL, 0); in cayman_gpu_init()
1301 WREG32(0x15D4, 0); in cayman_pcie_gart_enable()
1302 WREG32(0x15D8, 0); in cayman_pcie_gart_enable()
1303 WREG32(0x15DC, 0); in cayman_pcie_gart_enable()
1366 WREG32(VM_L2_CNTL2, 0); in cayman_pcie_gart_disable()
1451 WREG32(CP_ME_CNTL, 0); in cayman_cp_enable()
1456 WREG32(SCRATCH_UMSK, 0); in cayman_cp_enable()
[all …]
A Devergreen_hdmi.c65 WREG32(AZ_HOT_PLUG_CONTROL, tmp); in dce4_audio_enable()
214 WREG32(AFMT_AVI_INFO0 + offset, in evergreen_set_avi_packet()
216 WREG32(AFMT_AVI_INFO1 + offset, in evergreen_set_avi_packet()
218 WREG32(AFMT_AVI_INFO2 + offset, in evergreen_set_avi_packet()
220 WREG32(AFMT_AVI_INFO3 + offset, in evergreen_set_avi_packet()
253 WREG32(DCCG_AUDIO_DTO0_CNTL, value); in dce4_hdmi_audio_set_dto()
278 WREG32(DCCG_AUDIO_DTO1_CNTL, value); in dce4_dp_audio_set_dto()
352 WREG32(HDMI_CONTROL + offset, val); in dce4_hdmi_set_color_depth()
363 WREG32(AFMT_60958_0 + offset, in dce4_set_audio_packet()
366 WREG32(AFMT_60958_1 + offset, in dce4_set_audio_packet()
[all …]
A Devergreen.c2414 WREG32(VM_L2_CNTL2, 0); in evergreen_pcie_gart_enable()
2467 WREG32(VM_L2_CNTL2, 0); in evergreen_pcie_gart_disable()
2497 WREG32(VM_L2_CNTL2, 0); in evergreen_agp_enable()
2738 WREG32(BIF_FB_EN, 0); in evergreen_mc_stop()
2975 WREG32(CP_RB_CNTL, in evergreen_cp_load_microcode()
3103 WREG32(CP_RB_RPTR_ADDR, in evergreen_cp_resume()
3694 WREG32(i, 0); in evergreen_gpu_init()
3696 WREG32(i, 0); in evergreen_gpu_init()
4379 WREG32(RLC_CNTL, mask); in evergreen_rlc_start()
4392 WREG32(RLC_HB_CNTL, 0); in evergreen_rlc_resume()
[all …]
A Dradeon_legacy_encoders.c689 WREG32(RADEON_DAC_EXT_CNTL, tmp); in radeon_legacy_primary_dac_detect()
693 WREG32(RADEON_DAC_CNTL, tmp); in radeon_legacy_primary_dac_detect()
1328 WREG32(RADEON_CRTC2_GEN_CNTL, in r300_legacy_tv_detect()
1335 WREG32(RADEON_DAC_EXT_CNTL, in r300_legacy_tv_detect()
1341 WREG32(RADEON_TV_DAC_CNTL, in r300_legacy_tv_detect()
1349 WREG32(RADEON_TV_DAC_CNTL, in r300_legacy_tv_detect()
1397 WREG32(RADEON_DAC_CNTL2, tmp); in radeon_legacy_tv_detect()
1416 WREG32(RADEON_TV_DAC_CNTL, tmp); in radeon_legacy_tv_detect()
1473 WREG32(RADEON_GPIO_MONID, tmp); in radeon_legacy_ext_dac_detect()
1630 WREG32(RADEON_TV_DAC_CNTL, tmp); in radeon_legacy_tv_dac_detect()
[all …]
A Dcik.c243 WREG32(PCIE_INDEX, reg); in cik_pciep_rreg()
255 WREG32(PCIE_INDEX, reg); in cik_pciep_wreg()
257 WREG32(PCIE_DATA, v); in cik_pciep_wreg()
3358 WREG32(SQ_CONFIG, 1); in cik_gpu_init()
3360 WREG32(DB_DEBUG, 0); in cik_gpu_init()
3385 WREG32(SQ_CONFIG, 0); in cik_gpu_init()
5459 WREG32(0x15D4, 0); in cik_pcie_gart_enable()
5460 WREG32(0x15D8, 0); in cik_pcie_gart_enable()
5461 WREG32(0x15DC, 0); in cik_pcie_gart_enable()
5556 WREG32(VM_L2_CNTL, in cik_pcie_gart_disable()
[all …]
/linux/drivers/misc/habanalabs/gaudi/
A Dgaudi_coresight.c506 WREG32(base_reg + 0x20, 0); in gaudi_config_etf()
518 WREG32(base_reg + 0x20, 1); in gaudi_config_etf()
520 WREG32(base_reg + 0x34, 0); in gaudi_config_etf()
521 WREG32(base_reg + 0x28, 0); in gaudi_config_etf()
602 WREG32(mmPSOC_ETR_CTL, 0); in gaudi_config_etr()
647 WREG32(mmPSOC_ETR_DBALO, in gaudi_config_etr()
649 WREG32(mmPSOC_ETR_DBAHI, in gaudi_config_etr()
651 WREG32(mmPSOC_ETR_FFCR, 3); in gaudi_config_etr()
653 WREG32(mmPSOC_ETR_CTL, 1); in gaudi_config_etr()
659 WREG32(mmPSOC_ETR_PSCR, 0); in gaudi_config_etr()
[all …]
A Dgaudi.c3595 WREG32(mmNIC0_QM0_GLBL_CFG1, in gaudi_stop_nic_qmans()
3601 WREG32(mmNIC0_QM1_GLBL_CFG1, in gaudi_stop_nic_qmans()
4095 WREG32(mmCPU_IF_QUEUE_INIT, in gaudi_init_cpu_queues()
4102 WREG32(irq_handler_offset, in gaudi_init_cpu_queues()
4297 WREG32(irq_handler_offset, in gaudi_hw_fini()
4752 WREG32(irq_handler_offset, in gaudi_ring_doorbell()
8218 WREG32(mmSTLB_INV_PS, 3); in gaudi_mmu_invalidate_cache()
8220 WREG32(mmSTLB_INV_PS, 2); in gaudi_mmu_invalidate_cache()
8230 WREG32(mmSTLB_INV_SET, 0); in gaudi_mmu_invalidate_cache()
8262 WREG32(MMU_ASID, asid); in gaudi_mmu_update_asid_hop0_addr()
[all …]
/linux/drivers/gpu/drm/amd/amdgpu/
A Dgmc_v6_0.c73 WREG32(mmBIF_FB_EN, 0); in gmc_v6_0_mc_stop()
95 WREG32(mmBIF_FB_EN, tmp); in gmc_v6_0_mc_resume()
494 WREG32(mmVM_L2_CNTL, in gmc_v6_0_gart_enable()
501 WREG32(mmVM_L2_CNTL2, in gmc_v6_0_gart_enable()
506 WREG32(mmVM_L2_CNTL3, in gmc_v6_0_gart_enable()
522 WREG32(0x575, 0); in gmc_v6_0_gart_enable()
523 WREG32(0x576, 0); in gmc_v6_0_gart_enable()
524 WREG32(0x577, 0); in gmc_v6_0_gart_enable()
602 WREG32(mmVM_L2_CNTL, in gmc_v6_0_gart_disable()
607 WREG32(mmVM_L2_CNTL2, 0); in gmc_v6_0_gart_disable()
[all …]
A Dgmc_v8_0.c188 WREG32(mmBIF_FB_EN, 0); in gmc_v8_0_mc_stop()
209 WREG32(mmBIF_FB_EN, tmp); in gmc_v8_0_mc_resume()
792 WREG32(mmVM_PRT_CNTL, tmp); in gmc_v8_0_set_prt()
863 WREG32(mmVM_L2_CNTL, tmp); in gmc_v8_0_gart_enable()
867 WREG32(mmVM_L2_CNTL2, tmp); in gmc_v8_0_gart_enable()
993 WREG32(mmVM_L2_CNTL, tmp); in gmc_v8_0_gart_disable()
994 WREG32(mmVM_L2_CNTL2, 0); in gmc_v8_0_gart_disable()
1541 WREG32(mmVM_L2_CG, data); in fiji_update_mc_medium_grain_clock_gating()
1577 WREG32(mmVM_L2_CG, data); in fiji_update_mc_medium_grain_clock_gating()
1621 WREG32(mmVM_L2_CG, data); in fiji_update_mc_light_sleep()
[all …]
A Dvce_v3_0.c185 WREG32(mmVCE_CLOCK_GATING_B, data); in vce_v3_0_set_vce_sw_clock_gating()
211 WREG32(mmVCE_CLOCK_GATING_B, data); in vce_v3_0_set_vce_sw_clock_gating()
351 WREG32(mmVCE_STATUS, 0); in vce_v3_0_stop()
559 WREG32(mmVCE_CLOCK_GATING_B, 0x1FF); in vce_v3_0_mc_resume()
561 WREG32(mmVCE_LMI_CTRL, 0x00398000); in vce_v3_0_mc_resume()
563 WREG32(mmVCE_LMI_SWAP_CNTL, 0); in vce_v3_0_mc_resume()
564 WREG32(mmVCE_LMI_SWAP_CNTL1, 0); in vce_v3_0_mc_resume()
565 WREG32(mmVCE_LMI_VM_CTRL, 0); in vce_v3_0_mc_resume()
577 WREG32(mmVCE_VCPU_CACHE_SIZE0, size); in vce_v3_0_mc_resume()
688 WREG32(mmSRBM_SOFT_RESET, tmp); in vce_v3_0_soft_reset()
[all …]
A Dvce_v2_0.c144 WREG32(mmVCE_CGTT_CLK_OVERRIDE, 7); in vce_v2_0_disable_cg()
155 WREG32(mmVCE_CLOCK_GATING_A, tmp); in vce_v2_0_init_cg()
165 WREG32(mmVCE_CLOCK_GATING_B, tmp); in vce_v2_0_init_cg()
175 WREG32(mmVCE_CLOCK_GATING_B, 0xf7); in vce_v2_0_mc_resume()
177 WREG32(mmVCE_LMI_CTRL, 0x00398000); in vce_v2_0_mc_resume()
179 WREG32(mmVCE_LMI_SWAP_CNTL, 0); in vce_v2_0_mc_resume()
180 WREG32(mmVCE_LMI_SWAP_CNTL1, 0); in vce_v2_0_mc_resume()
181 WREG32(mmVCE_LMI_VM_CTRL, 0); in vce_v2_0_mc_resume()
305 WREG32(mmVCE_STATUS, 0); in vce_v2_0_stop()
317 WREG32(mmVCE_CLOCK_GATING_B, tmp); in vce_v2_0_set_sw_cg()
[all …]
A Dgmc_v7_0.c99 WREG32(mmBIF_FB_EN, 0); in gmc_v7_0_mc_stop()
120 WREG32(mmBIF_FB_EN, tmp); in gmc_v7_0_mc_resume()
296 WREG32(mmMC_VM_AGP_BASE, 0); in gmc_v7_0_mc_program()
575 WREG32(mmVM_PRT_CNTL, tmp); in gmc_v7_0_set_prt()
646 WREG32(mmVM_L2_CNTL, tmp); in gmc_v7_0_gart_enable()
649 WREG32(mmVM_L2_CNTL2, tmp); in gmc_v7_0_gart_enable()
670 WREG32(0x575, 0); in gmc_v7_0_gart_enable()
671 WREG32(0x576, 0); in gmc_v7_0_gart_enable()
672 WREG32(0x577, 0); in gmc_v7_0_gart_enable()
759 WREG32(mmVM_L2_CNTL, tmp); in gmc_v7_0_gart_disable()
[all …]
A Duvd_v5_0.c367 WREG32(mmUVD_MPC_SET_ALU, 0); in uvd_v5_0_start()
368 WREG32(mmUVD_MPC_SET_MUX, 0x88); in uvd_v5_0_start()
381 WREG32(mmUVD_SOFT_RESET, 0); in uvd_v5_0_start()
424 WREG32(mmUVD_RBC_RB_CNTL, tmp); in uvd_v5_0_start()
439 WREG32(mmUVD_RBC_RB_RPTR, 0); in uvd_v5_0_start()
470 WREG32(mmUVD_VCPU_CNTL, 0x0); in uvd_v5_0_stop()
475 WREG32(mmUVD_STATUS, 0); in uvd_v5_0_stop()
672 WREG32(mmUVD_CGC_GATE, data3); in uvd_v5_0_enable_clock_gating()
718 WREG32(mmUVD_CGC_CTRL, data); in uvd_v5_0_set_sw_clock_gating()
758 WREG32(mmUVD_CGC_GATE, data);
[all …]
A Duvd_v4_2.c292 WREG32(mmUVD_CGC_GATE, 0); in uvd_v4_2_start()
299 WREG32(mmUVD_VCPU_CNTL, 1 << 9); in uvd_v4_2_start()
312 WREG32(mmUVD_LMI_CTRL, 0x203108); in uvd_v4_2_start()
318 WREG32(mmUVD_MPC_SET_MUXA1, 0x0); in uvd_v4_2_start()
321 WREG32(mmUVD_MPC_SET_ALU, 0); in uvd_v4_2_start()
322 WREG32(mmUVD_MPC_SET_MUX, 0x88); in uvd_v4_2_start()
382 WREG32(mmUVD_RBC_RB_RPTR, 0x0); in uvd_v4_2_start()
457 WREG32(mmUVD_STATUS, 0); in uvd_v4_2_stop()
617 WREG32(mmUVD_CGC_CTRL, data); in uvd_v4_2_enable_mgcg()
626 WREG32(mmUVD_CGC_CTRL, data); in uvd_v4_2_enable_mgcg()
[all …]

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