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Searched refs:WREG32_SMC (Results 1 – 21 of 21) sorted by relevance

/linux/drivers/gpu/drm/radeon/
A Dtrinity_smc.c66 WREG32_SMC(SMU_SCRATCH0, 1); in trinity_dpm_config()
68 WREG32_SMC(SMU_SCRATCH0, 0); in trinity_dpm_config()
75 WREG32_SMC(SMU_SCRATCH0, n); in trinity_dpm_force_state()
82 WREG32_SMC(SMU_SCRATCH0, n); in trinity_dpm_n_levels_disabled()
A Dtrinity_dpm.c339 WREG32_SMC(GFX_POWER_GATING_CNTL, value); in trinity_gfx_powergating_initialize()
481 WREG32_SMC(PM_I_CNTL_1, value); in trinity_gfx_dynamic_mgpg_enable()
486 WREG32_SMC(SMU_S_PG_CNTL, value); in trinity_gfx_dynamic_mgpg_enable()
490 WREG32_SMC(SMU_S_PG_CNTL, value); in trinity_gfx_dynamic_mgpg_enable()
494 WREG32_SMC(PM_I_CNTL_1, value); in trinity_gfx_dynamic_mgpg_enable()
716 WREG32_SMC(SMU_SCLK_DPM_CNTL, value); in trinity_start_dpm()
849 WREG32_SMC(SMU_UVD_DPM_CNTL, val); in trinity_setup_uvd_dpm_interval()
969 WREG32_SMC(SMU_SCLK_DPM_TTT, value); in trinity_program_ttt()
978 WREG32_SMC(SMU_SCLK_DPM_TT_CNTL, value); in trinity_enable_att()
996 WREG32_SMC(PM_I_CNTL_1, value); in trinity_program_sclk_dpm()
[all …]
A Dci_smc.c119 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); in ci_start_smc()
127 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); in ci_reset_smc()
143 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp); in ci_stop_smc_clock()
152 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp); in ci_start_smc_clock()
A Dsi_smc.c119 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); in si_start_smc()
133 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); in si_reset_smc()
149 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp); in si_stop_smc_clock()
158 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp); in si_start_smc_clock()
A Dci_dpm.c925 WREG32_SMC(CG_FDO_CTRL2, tmp); in ci_fan_ctrl_set_static_mode()
929 WREG32_SMC(CG_FDO_CTRL2, tmp); in ci_fan_ctrl_set_static_mode()
1103 WREG32_SMC(CG_FDO_CTRL0, tmp); in ci_fan_ctrl_set_fan_speed_percent()
2046 WREG32_SMC(CG_FTV_0, 0); in ci_clear_vc()
2047 WREG32_SMC(CG_FTV_1, 0); in ci_clear_vc()
2048 WREG32_SMC(CG_FTV_2, 0); in ci_clear_vc()
2049 WREG32_SMC(CG_FTV_3, 0); in ci_clear_vc()
2050 WREG32_SMC(CG_FTV_4, 0); in ci_clear_vc()
2051 WREG32_SMC(CG_FTV_5, 0); in ci_clear_vc()
2052 WREG32_SMC(CG_FTV_6, 0); in ci_clear_vc()
[all …]
A Dkv_dpm.c191 WREG32_SMC(config_regs->offset, data); in kv_program_pt_config_registers()
368 WREG32_SMC(CG_FTV_0, 0x3FFFC100); in kv_program_vc()
373 WREG32_SMC(CG_FTV_0, 0); in kv_clear_vc()
491 WREG32_SMC(GENERAL_PWRMGT, tmp); in kv_start_dpm()
508 WREG32_SMC(SCLK_PWRMGT_CNTL, sclk_pwrmgt_cntl); in kv_start_am()
517 WREG32_SMC(SCLK_PWRMGT_CNTL, sclk_pwrmgt_cntl); in kv_reset_am()
1024 WREG32_SMC(CG_THERMAL_INT_CTRL, thermal_int); in kv_enable_thermal_int()
2245 WREG32_SMC(NB_DPM_CONFIG_1, nbdpmconfig1); in kv_program_nbps_index_settings()
2269 WREG32_SMC(CG_THERMAL_INT_CTRL, tmp); in kv_set_thermal_temperature_range()
A Dcik.c9422 WREG32_SMC(cntl_reg, tmp); in cik_set_uvd_clock()
9469 WREG32_SMC(CG_ECLK_CNTL, tmp); in cik_set_vce_clocks()
9768 WREG32_SMC(THM_CLK_CNTL, data); in cik_program_aspm()
9774 WREG32_SMC(MISC_CLK_CTRL, data); in cik_program_aspm()
9779 WREG32_SMC(CG_CLKPIN_CNTL, data); in cik_program_aspm()
9784 WREG32_SMC(CG_CLKPIN_CNTL_2, data); in cik_program_aspm()
9790 WREG32_SMC(MPLL_BYPASSCLK_SEL, data); in cik_program_aspm()
A Dsi.c5461 WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_0, 0); in si_enable_uvd_mgcg()
5462 WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_1, 0); in si_enable_uvd_mgcg()
5473 WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_0, 0xffffffff); in si_enable_uvd_mgcg()
5474 WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_1, 0xffffffff); in si_enable_uvd_mgcg()
A Dradeon.h2562 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v)) macro
2596 WREG32_SMC(reg, tmp_); \
A Dsi_dpm.c2744 WREG32_SMC(offset, data); in si_program_cac_config_registers()
/linux/drivers/gpu/drm/amd/pm/powerplay/
A Dsi_smc.c117 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); in amdgpu_si_start_smc()
131 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); in amdgpu_si_reset_smc()
150 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp); in amdgpu_si_smc_clock()
A Dkv_dpm.c534 WREG32_SMC(ixLCAC_SX0_OVR_SEL, 0);
535 WREG32_SMC(ixLCAC_SX0_OVR_VAL, 0);
538 WREG32_SMC(ixLCAC_MC0_OVR_SEL, 0);
539 WREG32_SMC(ixLCAC_MC0_OVR_VAL, 0);
542 WREG32_SMC(ixLCAC_MC1_OVR_SEL, 0);
543 WREG32_SMC(ixLCAC_MC1_OVR_VAL, 0);
546 WREG32_SMC(ixLCAC_MC2_OVR_SEL, 0);
547 WREG32_SMC(ixLCAC_MC2_OVR_VAL, 0);
550 WREG32_SMC(ixLCAC_MC3_OVR_SEL, 0);
551 WREG32_SMC(ixLCAC_MC3_OVR_VAL, 0);
[all …]
A Dsi_dpm.c2845 WREG32_SMC(offset, data); in si_program_cac_config_registers()
7514 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int); in si_dpm_set_interrupt_state()
7519 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int); in si_dpm_set_interrupt_state()
7531 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int); in si_dpm_set_interrupt_state()
7536 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int); in si_dpm_set_interrupt_state()
/linux/drivers/gpu/drm/amd/amdgpu/
A Dcik.c997 WREG32_SMC(ixROM_CNTL, rom_cntl | ROM_CNTL__SCK_OVERWRITE_MASK); in cik_read_disabled_bios()
1008 WREG32_SMC(ixROM_CNTL, rom_cntl); in cik_read_disabled_bios()
1464 WREG32_SMC(cntl_reg, tmp); in cik_set_uvd_clock()
1513 WREG32_SMC(ixCG_ECLK_CNTL, tmp); in cik_set_vce_clocks()
1824 WREG32_SMC(ixTHM_CLK_CNTL, data); in cik_program_aspm()
1832 WREG32_SMC(ixMISC_CLK_CTRL, data); in cik_program_aspm()
1837 WREG32_SMC(ixCG_CLKPIN_CNTL, data); in cik_program_aspm()
1842 WREG32_SMC(ixCG_CLKPIN_CNTL_2, data); in cik_program_aspm()
1848 WREG32_SMC(ixMPLL_BYPASSCLK_SEL, data); in cik_program_aspm()
A Dvi.c618 WREG32_SMC(ixROM_CNTL, rom_cntl | ROM_CNTL__SCK_OVERWRITE_MASK); in vi_read_disabled_bios()
629 WREG32_SMC(ixROM_CNTL, rom_cntl); in vi_read_disabled_bios()
996 WREG32_SMC(cntl_reg, tmp); in vi_set_uvd_clock()
1086 WREG32_SMC(reg_ctrl, tmp); in vi_set_vce_clocks()
1205 WREG32_SMC(ixTHM_CLK_CNTL, data); in vi_program_aspm()
1214 WREG32_SMC(ixMISC_CLK_CTRL, data); in vi_program_aspm()
1219 WREG32_SMC(ixCG_CLKPIN_CNTL, data); in vi_program_aspm()
1224 WREG32_SMC(ixCG_CLKPIN_CNTL, data); in vi_program_aspm()
1230 WREG32_SMC(ixMPLL_BYPASSCLK_SEL, data); in vi_program_aspm()
1863 WREG32_SMC(ixCGTT_ROM_CLK_CTRL0, data); in vi_update_rom_medium_grain_clock_gating()
A Damdgpu_cgs.c94 return WREG32_SMC(index, value); in amdgpu_cgs_write_ind_register()
A Damdgpu.h1193 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) macro
1226 WREG32_SMC(_Reg, tmp); \
A Dvce_v4_0.c915 WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);
A Damdgpu_debugfs.c686 WREG32_SMC(*pos, value); in amdgpu_debugfs_regs_smc_write()
A Duvd_v7_0.c1715 WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);
A Dgfx_v8_0.c802 WREG32_SMC(ixCG_ACLK_CNTL, data); in gfx_v8_0_init_golden_registers()

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