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Searched refs:_shift (Results 1 – 25 of 159) sorted by relevance

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/linux/drivers/iio/dac/
A Dad5686.c203 .shift = (_shift), \
210 AD5868_CHANNEL(0, 0, bits, _shift), \
215 AD5868_CHANNEL(0, 1, bits, _shift), \
216 AD5868_CHANNEL(1, 8, bits, _shift), \
221 AD5868_CHANNEL(0, 1, bits, _shift), \
222 AD5868_CHANNEL(1, 2, bits, _shift), \
223 AD5868_CHANNEL(2, 4, bits, _shift), \
224 AD5868_CHANNEL(3, 8, bits, _shift), \
229 AD5868_CHANNEL(0, 0, bits, _shift), \
230 AD5868_CHANNEL(1, 1, bits, _shift), \
[all …]
/linux/drivers/clk/sunxi-ng/
A Dccu_div.h45 .shift = _shift, \
56 .shift = _shift, \
67 _SUNXI_CCU_DIV_MAX_FLAGS(_shift, _width, 0, _flags)
69 #define _SUNXI_CCU_DIV_MAX(_shift, _width, _max) \ argument
70 _SUNXI_CCU_DIV_MAX_FLAGS(_shift, _width, _max, 0)
75 #define _SUNXI_CCU_DIV(_shift, _width) \ argument
76 _SUNXI_CCU_DIV_FLAGS(_shift, _width, 0)
88 _shift, _width, \ argument
91 .div = _SUNXI_CCU_DIV_TABLE(_shift, _width, \
105 _shift, _width, \ argument
[all …]
A Dccu_mux.h32 #define _SUNXI_CCU_MUX_TABLE(_shift, _width, _table) \ argument
34 .shift = _shift, \
39 #define _SUNXI_CCU_MUX(_shift, _width) \ argument
40 _SUNXI_CCU_MUX_TABLE(_shift, _width, NULL)
50 _reg, _shift, _width, _gate, \ argument
54 .mux = _SUNXI_CCU_MUX_TABLE(_shift, _width, _table), \
65 _shift, _width, _gate, _flags) \ argument
67 _reg, _shift, _width, _gate, \
70 #define SUNXI_CCU_MUX(_struct, _name, _parents, _reg, _shift, _width, \ argument
73 _reg, _shift, _width, 0, _flags)
A Dccu_mult.h17 #define _SUNXI_CCU_MULT_OFFSET_MIN_MAX(_shift, _width, _offset, _min, _max) \ argument
22 .shift = _shift, \
26 #define _SUNXI_CCU_MULT_MIN(_shift, _width, _min) \ argument
27 _SUNXI_CCU_MULT_OFFSET_MIN_MAX(_shift, _width, 1, _min, 0)
29 #define _SUNXI_CCU_MULT_OFFSET(_shift, _width, _offset) \ argument
30 _SUNXI_CCU_MULT_OFFSET_MIN_MAX(_shift, _width, _offset, 1, 0)
32 #define _SUNXI_CCU_MULT(_shift, _width) \ argument
33 _SUNXI_CCU_MULT_OFFSET_MIN_MAX(_shift, _width, 1, 1, 0)
/linux/drivers/clk/mediatek/
A Dclk-mt8195-infra_ao.c44 GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao0_cg_regs, _shift, \
47 #define GATE_INFRA_AO0(_id, _name, _parent, _shift) \ argument
48 GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, 0)
51 GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao1_cg_regs, _shift, \
54 #define GATE_INFRA_AO1(_id, _name, _parent, _shift) \ argument
55 GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, 0)
57 #define GATE_INFRA_AO2(_id, _name, _parent, _shift) \ argument
64 #define GATE_INFRA_AO3(_id, _name, _parent, _shift) \ argument
65 GATE_INFRA_AO3_FLAGS(_id, _name, _parent, _shift, 0)
71 #define GATE_INFRA_AO4(_id, _name, _parent, _shift) \ argument
[all …]
A Dclk-mt8183-ipu_conn.c44 #define GATE_IPU_CONN(_id, _name, _parent, _shift) \ argument
45 GATE_MTK(_id, _name, _parent, &ipu_conn_cg_regs, _shift, \
48 #define GATE_IPU_CONN_APB(_id, _name, _parent, _shift) \ argument
49 GATE_MTK(_id, _name, _parent, &ipu_conn_apb_cg_regs, _shift, \
52 #define GATE_IPU_CONN_AXI_I(_id, _name, _parent, _shift) \ argument
53 GATE_MTK(_id, _name, _parent, &ipu_conn_axi_cg_regs, _shift, \
56 #define GATE_IPU_CONN_AXI1_I(_id, _name, _parent, _shift) \ argument
57 GATE_MTK(_id, _name, _parent, &ipu_conn_axi1_cg_regs, _shift, \
60 #define GATE_IPU_CONN_AXI2_I(_id, _name, _parent, _shift) \ argument
61 GATE_MTK(_id, _name, _parent, &ipu_conn_axi2_cg_regs, _shift, \
A Dclk-mtk.h82 #define MUX_GATE_FLAGS_2(_id, _name, _parents, _reg, _shift, \ argument
87 .mux_shift = _shift, \
102 #define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \ argument
105 _shift, _width, _gate, _flags, 0)
111 #define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate) \ argument
112 MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \
115 #define MUX(_id, _name, _parents, _reg, _shift, _width) \ argument
117 _shift, _width, CLK_SET_RATE_PARENT)
123 .mux_shift = _shift, \
191 #define DIV_ADJ(_id, _name, _parent, _reg, _shift, _width) { \ argument
[all …]
A Dclk-mux.h41 _mux_set_ofs, _mux_clr_ofs, _shift, _width, \ argument
49 .mux_shift = _shift, \
63 _mux_set_ofs, _mux_clr_ofs, _shift, _width, \ argument
66 _mux_set_ofs, _mux_clr_ofs, _shift, _width, \
71 _mux_set_ofs, _mux_clr_ofs, _shift, _width, \ argument
74 _mux_ofs, _mux_set_ofs, _mux_clr_ofs, _shift, \
79 _mux_set_ofs, _mux_clr_ofs, _shift, _width, \ argument
82 _mux_set_ofs, _mux_clr_ofs, _shift, _width, \
A Dclk-mt8192.c923 #define GATE_INFRA0(_id, _name, _parent, _shift) \ argument
930 #define GATE_INFRA1(_id, _name, _parent, _shift) \ argument
931 GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, 0)
933 #define GATE_INFRA2(_id, _name, _parent, _shift) \ argument
940 #define GATE_INFRA3(_id, _name, _parent, _shift) \ argument
941 GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, 0)
943 #define GATE_INFRA4(_id, _name, _parent, _shift) \ argument
950 #define GATE_INFRA5(_id, _name, _parent, _shift) \ argument
951 GATE_INFRA5_FLAGS(_id, _name, _parent, _shift, 0)
1095 #define GATE_PERI(_id, _name, _parent, _shift) \ argument
[all …]
A Dclk-mt8195-vdo1.c37 #define GATE_VDO1_0(_id, _name, _parent, _shift) \ argument
38 GATE_MTK(_id, _name, _parent, &vdo1_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
40 #define GATE_VDO1_1(_id, _name, _parent, _shift) \ argument
41 GATE_MTK(_id, _name, _parent, &vdo1_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
43 #define GATE_VDO1_2(_id, _name, _parent, _shift) \ argument
44 GATE_MTK(_id, _name, _parent, &vdo1_2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
46 #define GATE_VDO1_3(_id, _name, _parent, _shift) \ argument
47 GATE_MTK(_id, _name, _parent, &vdo1_3_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
A Dclk-mt8192-vdec.c33 #define GATE_VDEC0(_id, _name, _parent, _shift) \ argument
34 GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
36 #define GATE_VDEC1(_id, _name, _parent, _shift) \ argument
37 GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
39 #define GATE_VDEC2(_id, _name, _parent, _shift) \ argument
40 GATE_MTK(_id, _name, _parent, &vdec2_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
A Dclk-mt8167.c662 .div_shift = _shift, \
692 .div_shift = _shift, \
738 #define GATE_TOP0(_id, _name, _parent, _shift) { \ argument
743 .shift = _shift, \
752 .shift = _shift, \
761 .shift = _shift, \
770 .shift = _shift, \
779 .shift = _shift, \
788 .shift = _shift, \
797 .shift = _shift, \
[all …]
A Dclk-mt8195-vdec.c31 #define GATE_VDEC0(_id, _name, _parent, _shift) \ argument
32 GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
34 #define GATE_VDEC1(_id, _name, _parent, _shift) \ argument
35 GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
37 #define GATE_VDEC2(_id, _name, _parent, _shift) \ argument
38 GATE_MTK(_id, _name, _parent, &vdec2_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
A Dclk-mt2701-aud.c18 #define GATE_AUDIO0(_id, _name, _parent, _shift) { \ argument
23 .shift = _shift, \
27 #define GATE_AUDIO1(_id, _name, _parent, _shift) { \ argument
32 .shift = _shift, \
36 #define GATE_AUDIO2(_id, _name, _parent, _shift) { \ argument
41 .shift = _shift, \
45 #define GATE_AUDIO3(_id, _name, _parent, _shift) { \ argument
50 .shift = _shift, \
A Dclk-mt7622-aud.c19 #define GATE_AUDIO0(_id, _name, _parent, _shift) { \ argument
24 .shift = _shift, \
28 #define GATE_AUDIO1(_id, _name, _parent, _shift) { \ argument
33 .shift = _shift, \
37 #define GATE_AUDIO2(_id, _name, _parent, _shift) { \ argument
42 .shift = _shift, \
46 #define GATE_AUDIO3(_id, _name, _parent, _shift) { \ argument
51 .shift = _shift, \
A Dclk-mt8192-mm.c32 #define GATE_MM0(_id, _name, _parent, _shift) \ argument
33 GATE_MTK(_id, _name, _parent, &mm0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
35 #define GATE_MM1(_id, _name, _parent, _shift) \ argument
36 GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
38 #define GATE_MM2(_id, _name, _parent, _shift) \ argument
39 GATE_MTK(_id, _name, _parent, &mm2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
A Dclk-mt8195-vpp0.c31 #define GATE_VPP0_0(_id, _name, _parent, _shift) \ argument
32 GATE_MTK(_id, _name, _parent, &vpp0_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
34 #define GATE_VPP0_1(_id, _name, _parent, _shift) \ argument
35 GATE_MTK(_id, _name, _parent, &vpp0_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
37 #define GATE_VPP0_2(_id, _name, _parent, _shift) \ argument
38 GATE_MTK(_id, _name, _parent, &vpp0_2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
A Dclk-mt8192-aud.c33 #define GATE_AUD0(_id, _name, _parent, _shift) \ argument
34 GATE_MTK(_id, _name, _parent, &aud0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
36 #define GATE_AUD1(_id, _name, _parent, _shift) \ argument
37 GATE_MTK(_id, _name, _parent, &aud1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
39 #define GATE_AUD2(_id, _name, _parent, _shift) \ argument
40 GATE_MTK(_id, _name, _parent, &aud2_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
A Dclk-mt8195-vdo0.c31 #define GATE_VDO0_0(_id, _name, _parent, _shift) \ argument
32 GATE_MTK(_id, _name, _parent, &vdo0_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
34 #define GATE_VDO0_1(_id, _name, _parent, _shift) \ argument
35 GATE_MTK(_id, _name, _parent, &vdo0_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
37 #define GATE_VDO0_2(_id, _name, _parent, _shift) \ argument
38 GATE_MTK(_id, _name, _parent, &vdo0_2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
A Dclk-mt8195-wpe.c31 #define GATE_WPE(_id, _name, _parent, _shift) \ argument
32 GATE_MTK(_id, _name, _parent, &wpe_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
34 #define GATE_WPE_VPP0(_id, _name, _parent, _shift) \ argument
35 GATE_MTK(_id, _name, _parent, &wpe_vpp0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
37 #define GATE_WPE_VPP1(_id, _name, _parent, _shift) \ argument
38 GATE_MTK(_id, _name, _parent, &wpe_vpp1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
/linux/drivers/clk/sprd/
A Dmux.h32 #define _SPRD_MUX_CLK(_shift, _width, _table) \ argument
34 .shift = _shift, \
40 _reg, _shift, _width, _flags, _fn) \ argument
52 _reg, _shift, _width, _flags) \ argument
54 _reg, _shift, _width, _flags, \
58 _shift, _width, _flags) \ argument
60 _reg, _shift, _width, _flags)
63 _reg, _shift, _width, _flags) \ argument
65 _reg, _shift, _width, _flags, \
69 _shift, _width, _flags) \ argument
[all …]
A Ddiv.h27 #define _SPRD_DIV_CLK(_shift, _width) \ argument
29 .shift = _shift, \
39 _shift, _width, _flags, _fn) \ argument
41 .div = _SPRD_DIV_CLK(_shift, _width), \
51 _shift, _width, _flags) \ argument
53 _shift, _width, _flags, CLK_HW_INIT)
56 _shift, _width, _flags) \ argument
58 _shift, _width, _flags, CLK_HW_INIT_HW)
/linux/drivers/clk/actions/
A Dowl-pll.h41 #define OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \ argument
47 .shift = _shift, \
56 _shift, _width, _min_mul, _max_mul, _table, _flags) \ argument
58 .pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \
71 _shift, _width, _min_mul, _max_mul, _table, _flags) \ argument
73 .pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \
85 _shift, _width, _min_mul, _max_mul, _delay, _table, \ argument
88 .pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \
/linux/drivers/net/ethernet/mellanox/mlxsw/
A Dcore_acl_flex_keys.h52 #define MLXSW_AFK_ELEMENT_INFO(_type, _element, _offset, _shift, _size) \ argument
58 .shift = _shift, \
64 #define MLXSW_AFK_ELEMENT_INFO_U32(_element, _offset, _shift, _size) \ argument
66 _element, _offset, _shift, _size)
85 _shift, _size, _u32_key_diff, _avoid_size_check) \ argument
91 .shift = _shift, \
99 #define MLXSW_AFK_ELEMENT_INST_U32(_element, _offset, _shift, _size) \ argument
101 _element, _offset, _shift, _size, 0, false)
104 _shift, _size, _key_diff, \ argument
107 _element, _offset, _shift, _size, \
/linux/drivers/clk/x86/
A Dclk-cgu.h207 _shift, _width, _cf, _v) \ argument
216 .mux_shift = _shift, \
222 #define LGM_DIV(_id, _name, _pname, _f, _reg, _shift, _width, \ argument
235 .div_shift = _shift, \
245 _shift, _cf, _v) \ argument
257 .gate_shift = _shift, \
263 _shift, _width, _cf, _freq, _v) \ argument
275 .div_shift = _shift, \
283 _shift, _width, _cf, _v, _m, _d) \ argument
295 .div_shift = _shift, \

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