| /linux/drivers/gpu/drm/amd/amdgpu/ |
| A D | amdgpu_virt.h | 250 #define amdgpu_sriov_vf(adev) \ macro
260 (amdgpu_sriov_vf((adev)) && !amdgpu_sriov_runtime((adev)))
263 (amdgpu_sriov_vf((adev)) && \
267 (amdgpu_sriov_vf((adev)) && \
271 (amdgpu_sriov_vf((adev)) && \
275 (amdgpu_sriov_vf((adev)) && \
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| A D | psp_v11_0_8.c | 63 if (amdgpu_sriov_vf(adev)) { in psp_v11_0_8_ring_stop()
94 if (amdgpu_sriov_vf(adev)) { in psp_v11_0_8_ring_create()
176 if (amdgpu_sriov_vf(adev)) in psp_v11_0_8_ring_get_wptr()
188 if (amdgpu_sriov_vf(adev)) { in psp_v11_0_8_ring_set_wptr()
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| A D | amdgpu_psp.c | 73 if (amdgpu_sriov_vf(adev)) { in psp_check_pmfw_centralized_cstate_management()
276 if (!amdgpu_sriov_vf(adev)) { in psp_sw_init()
534 if (amdgpu_sriov_vf(psp->adev)) in psp_prep_tmr_cmd_buf()
655 if (amdgpu_sriov_vf(psp->adev)) in psp_prep_tmr_unload_cmd_buf()
703 if (amdgpu_sriov_vf(psp->adev)) in psp_get_fw_attestation_records_addr()
729 if (amdgpu_sriov_vf(adev)) in psp_boot_config_get()
754 if (amdgpu_sriov_vf(adev)) in psp_boot_config_set()
855 if (amdgpu_sriov_vf(psp->adev)) in psp_asd_terminate()
1419 if (amdgpu_sriov_vf(adev)) in psp_ras_initialize()
1949 if (!amdgpu_sriov_vf(adev)) { in psp_hw_start()
[all …]
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| A D | psp_v3_1.c | 229 if (amdgpu_sriov_vf(adev)) { in psp_v3_1_ring_create()
291 if (amdgpu_sriov_vf(adev)) in psp_v3_1_ring_stop()
302 if (amdgpu_sriov_vf(adev)) in psp_v3_1_ring_stop()
378 if (amdgpu_sriov_vf(adev)) in psp_v3_1_ring_get_wptr()
389 if (amdgpu_sriov_vf(adev)) { in psp_v3_1_ring_set_wptr()
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| A D | mmhub_v1_0.c | 113 if (amdgpu_sriov_vf(adev)) in mmhub_v1_0_init_system_aperture_regs()
159 if (amdgpu_sriov_vf(adev)) in mmhub_v1_0_init_cache_regs()
210 if (amdgpu_sriov_vf(adev)) in mmhub_v1_0_disable_identity_aperture()
301 if (amdgpu_sriov_vf(adev)) in mmhub_v1_0_update_power_gating()
312 if (amdgpu_sriov_vf(adev)) { in mmhub_v1_0_gart_enable()
358 if (!amdgpu_sriov_vf(adev)) { in mmhub_v1_0_gart_disable()
377 if (amdgpu_sriov_vf(adev)) in mmhub_v1_0_set_fault_enable_default()
528 if (amdgpu_sriov_vf(adev)) in mmhub_v1_0_set_clockgating()
553 if (amdgpu_sriov_vf(adev)) in mmhub_v1_0_get_clockgating()
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| A D | psp_v12_0.c | 265 if (amdgpu_sriov_vf(psp->adev)) { in psp_v12_0_ring_create()
317 if (amdgpu_sriov_vf(adev)) in psp_v12_0_ring_stop()
328 if (amdgpu_sriov_vf(adev)) in psp_v12_0_ring_stop()
395 if (amdgpu_sriov_vf(adev)) in psp_v12_0_ring_get_wptr()
407 if (amdgpu_sriov_vf(adev)) { in psp_v12_0_ring_set_wptr()
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| A D | athub_v1_0.c | 68 if (amdgpu_sriov_vf(adev)) in athub_v1_0_set_clockgating()
93 if (amdgpu_sriov_vf(adev)) in athub_v1_0_get_clockgating()
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| A D | nv.c | 187 if (amdgpu_sriov_vf(adev)) { in nv_query_video_codecs()
735 if (!amdgpu_sriov_vf(adev)) { in nv_common_early_init()
831 if (amdgpu_sriov_vf(adev)) in nv_common_early_init()
852 if (amdgpu_sriov_vf(adev)) { in nv_common_early_init()
981 if (amdgpu_sriov_vf(adev)) { in nv_common_early_init()
993 if (amdgpu_sriov_vf(adev)) { in nv_common_late_init()
1007 if (amdgpu_sriov_vf(adev)) in nv_common_sw_init()
1038 if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev)) in nv_common_hw_init()
1090 if (amdgpu_sriov_vf(adev)) in nv_common_set_clockgating_state()
1127 if (amdgpu_sriov_vf(adev)) in nv_common_get_clockgating_state()
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| A D | psp_v13_0.c | 251 if (amdgpu_sriov_vf(adev)) { in psp_v13_0_ring_stop()
282 if (amdgpu_sriov_vf(adev)) { in psp_v13_0_ring_create()
364 if (amdgpu_sriov_vf(adev)) in psp_v13_0_ring_get_wptr()
376 if (amdgpu_sriov_vf(adev)) { in psp_v13_0_ring_set_wptr()
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| A D | amdgpu_device.c | 1192 if (amdgpu_sriov_vf(adev)) in amdgpu_device_resize_fb_bar()
1267 if (amdgpu_sriov_vf(adev)) in amdgpu_device_need_post()
2077 if (amdgpu_sriov_vf(adev)) { in amdgpu_device_ip_early_init()
2349 if (amdgpu_sriov_vf(adev)) in amdgpu_device_ip_init()
2404 if (amdgpu_sriov_vf(adev)) in amdgpu_device_ip_init()
2947 if (amdgpu_sriov_vf(adev)) in amdgpu_device_ip_suspend()
3321 if (amdgpu_sriov_vf(adev)) in amdgpu_device_get_job_timeout_settings()
3551 if (amdgpu_sriov_vf(adev)) in amdgpu_device_init()
3748 if (amdgpu_sriov_vf(adev)) in amdgpu_device_init()
4076 if (amdgpu_sriov_vf(adev)) in amdgpu_device_ip_check_soft_reset()
[all …]
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| A D | sdma_v5_0.c | 208 if (amdgpu_sriov_vf(adev)) in sdma_v5_0_init_golden_registers()
658 if (!amdgpu_sriov_vf(adev)) { in sdma_v5_0_ctx_switch_enable()
672 if (!amdgpu_sriov_vf(adev)) in sdma_v5_0_ctx_switch_enable()
696 if (amdgpu_sriov_vf(adev)) in sdma_v5_0_enable()
731 if (!amdgpu_sriov_vf(adev)) in sdma_v5_0_gfx_resume()
808 if (amdgpu_sriov_vf(adev)) in sdma_v5_0_gfx_resume()
943 if (amdgpu_sriov_vf(adev)) { in sdma_v5_0_start()
1388 if (amdgpu_sriov_vf(adev)) in sdma_v5_0_hw_fini()
1504 if (!amdgpu_sriov_vf(adev)) { in sdma_v5_0_set_trap_irq_state()
1634 if (amdgpu_sriov_vf(adev)) in sdma_v5_0_set_clockgating_state()
[all …]
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| A D | gmc_v9_0.c | 573 if (amdgpu_sriov_vf(adev)) in gmc_v9_0_process_interrupt()
663 if (!amdgpu_sriov_vf(adev) && in gmc_v9_0_set_irq_funcs()
704 (!amdgpu_sriov_vf(adev)) && in gmc_v9_0_use_invalidate_semaphore()
768 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) && in gmc_v9_0_flush_gpu_tlb()
1294 if (!amdgpu_sriov_vf(adev) && in gmc_v9_0_late_init()
1491 if (amdgpu_sriov_vf(adev)) in gmc_v9_0_sw_init()
1543 if (amdgpu_sriov_vf(adev)) in gmc_v9_0_sw_init()
1577 if (!amdgpu_sriov_vf(adev) && in gmc_v9_0_sw_init()
1660 if (amdgpu_sriov_vf(adev)) in gmc_v9_0_init_golden_registers()
1770 if (!amdgpu_sriov_vf(adev)) { in gmc_v9_0_hw_init()
[all …]
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| A D | amdgpu_vf_error.c | 36 if (!amdgpu_sriov_vf(adev)) in amdgpu_vf_error_put()
57 if ((NULL == adev) || (!amdgpu_sriov_vf(adev)) || in amdgpu_vf_error_trans_all()
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| A D | mmhub_v2_0.c | 225 if (!amdgpu_sriov_vf(adev)) { in mmhub_v2_0_init_system_aperture_regs()
283 if (amdgpu_sriov_vf(adev)) in mmhub_v2_0_init_cache_regs()
344 if (amdgpu_sriov_vf(adev)) in mmhub_v2_0_disable_identity_aperture()
480 if (amdgpu_sriov_vf(adev)) in mmhub_v2_0_set_fault_enable_default()
664 if (amdgpu_sriov_vf(adev)) in mmhub_v2_0_set_clockgating()
689 if (amdgpu_sriov_vf(adev)) in mmhub_v2_0_get_clockgating()
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| A D | psp_v11_0.c | 180 if (amdgpu_sriov_vf(adev)) in psp_v11_0_init_microcode()
444 if (amdgpu_sriov_vf(adev)) in psp_v11_0_ring_stop()
455 if (amdgpu_sriov_vf(adev)) in psp_v11_0_ring_stop()
473 if (amdgpu_sriov_vf(adev)) { in psp_v11_0_ring_create()
746 if (amdgpu_sriov_vf(adev)) in psp_v11_0_ring_get_wptr()
758 if (amdgpu_sriov_vf(adev)) { in psp_v11_0_ring_set_wptr()
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| A D | soc15.c | 974 if (!amdgpu_sriov_vf(adev)) { in soc15_common_early_init()
1211 if (amdgpu_sriov_vf(adev)) { in soc15_common_early_init()
1224 if (amdgpu_sriov_vf(adev)) in soc15_common_late_init()
1238 if (amdgpu_sriov_vf(adev)) in soc15_common_sw_init()
1263 if (!amdgpu_sriov_vf(adev)) { in soc15_doorbell_range_init()
1290 if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev)) in soc15_common_hw_init()
1311 if (amdgpu_sriov_vf(adev)) in soc15_common_hw_fini()
1405 if (amdgpu_sriov_vf(adev)) in soc15_common_set_clockgating_state()
1457 if (amdgpu_sriov_vf(adev)) in soc15_common_get_clockgating_state()
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| A D | gmc_v10_0.c | 129 if (!amdgpu_sriov_vf(adev)) { in gmc_v10_0_process_interrupt()
160 if (!amdgpu_sriov_vf(adev)) in gmc_v10_0_process_interrupt()
182 if (!amdgpu_sriov_vf(adev)) { in gmc_v10_0_set_irq_funcs()
200 (!amdgpu_sriov_vf(adev))); in gmc_v10_0_use_invalidate_semaphore()
330 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) && in gmc_v10_0_flush_gpu_tlb()
897 if (!amdgpu_sriov_vf(adev)) { in gmc_v10_0_sw_init()
1074 if (amdgpu_sriov_vf(adev)) { in gmc_v10_0_hw_fini()
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| A D | amdgpu_virt.c | 216 if (!amdgpu_sriov_vf(adev) || adev->virt.mm_table.gpu_addr) in amdgpu_virt_alloc_mm_table()
243 if (!amdgpu_sriov_vf(adev) || !adev->virt.mm_table.gpu_addr) in amdgpu_virt_free_mm_table()
706 if (amdgpu_sriov_vf(adev)) { in amdgpu_detect_virtualization()
744 if (!amdgpu_sriov_vf(adev) || in amdgpu_virt_enable_access_debugfs()
758 if (amdgpu_sriov_vf(adev)) in amdgpu_virt_disable_access_debugfs()
766 if (amdgpu_sriov_vf(adev)) { in amdgpu_virt_get_sriov_vf_mode()
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| A D | navi10_ih.c | 123 if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) { in force_update_wptr_for_self_int()
133 if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) { in force_update_wptr_for_self_int()
168 if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) { in navi10_ih_toggle_ring_interrupts()
282 if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) { in navi10_ih_enable_ring()
491 if (amdgpu_sriov_vf(adev)) in navi10_ih_set_rptr()
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| A D | gfxhub_v1_0.c | 100 if (!amdgpu_sriov_vf(adev) || adev->asic_type <= CHIP_VEGA10) { in gfxhub_v1_0_init_system_aperture_regs()
327 if (!amdgpu_sriov_vf(adev)) in gfxhub_v1_0_gart_enable()
331 if (!amdgpu_sriov_vf(adev)) in gfxhub_v1_0_gart_enable()
350 if (amdgpu_sriov_vf(adev)) in gfxhub_v1_0_gart_disable()
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| A D | vi.c | 490 if (amdgpu_sriov_vf(adev)) { in vi_init_golden_registers()
1688 if (amdgpu_sriov_vf(adev)) { in vi_common_early_init()
1700 if (amdgpu_sriov_vf(adev)) in vi_common_late_init()
1710 if (amdgpu_sriov_vf(adev)) in vi_common_sw_init()
1744 if (amdgpu_sriov_vf(adev)) in vi_common_hw_fini()
1988 if (amdgpu_sriov_vf(adev)) in vi_common_set_clockgating_state()
2037 if (amdgpu_sriov_vf(adev)) in vi_common_get_clockgating_state()
2114 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) in vi_set_ip_blocks()
2122 if (!amdgpu_sriov_vf(adev)) { in vi_set_ip_blocks()
2134 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) in vi_set_ip_blocks()
[all …]
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| A D | vcn_v2_0.c | 72 if (amdgpu_sriov_vf(adev)) in vcn_v2_0_early_init()
158 if (!amdgpu_sriov_vf(adev)) in vcn_v2_0_sw_init()
225 if (amdgpu_sriov_vf(adev)) in vcn_v2_0_hw_init()
233 if (amdgpu_sriov_vf(adev)) in vcn_v2_0_hw_init()
326 if (amdgpu_sriov_vf(adev)) in vcn_v2_0_mc_resume()
484 if (amdgpu_sriov_vf(adev)) in vcn_v2_0_disable_clock_gating()
644 if (amdgpu_sriov_vf(adev)) in vcn_v2_0_enable_clock_gating()
698 if (amdgpu_sriov_vf(adev)) in vcn_v2_0_disable_static_power_gating()
747 if (amdgpu_sriov_vf(adev)) in vcn_v2_0_enable_static_power_gating()
1292 if (amdgpu_sriov_vf(adev)) in vcn_v2_0_set_clockgating_state()
[all …]
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| A D | gfxhub_v2_1.c | 213 if (amdgpu_sriov_vf(adev)) in gfxhub_v2_1_init_cache_regs()
274 if (amdgpu_sriov_vf(adev)) in gfxhub_v2_1_disable_identity_aperture()
354 if (amdgpu_sriov_vf(adev)) { in gfxhub_v2_1_gart_enable()
417 if (amdgpu_sriov_vf(adev)) in gfxhub_v2_1_set_fault_enable_default()
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| A D | sdma_v5_2.c | 177 if (amdgpu_sriov_vf(adev) && (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 2, 0))) in sdma_v5_2_init_microcode()
662 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */ in sdma_v5_2_gfx_resume()
684 if (amdgpu_sriov_vf(adev)) in sdma_v5_2_gfx_resume()
713 if (!amdgpu_sriov_vf(adev)) { in sdma_v5_2_gfx_resume()
734 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */ in sdma_v5_2_gfx_resume()
852 if (amdgpu_sriov_vf(adev)) { in sdma_v5_2_start()
1333 if (amdgpu_sriov_vf(adev)) in sdma_v5_2_hw_fini()
1604 if (amdgpu_sriov_vf(adev)) in sdma_v5_2_set_clockgating_state()
1637 if (amdgpu_sriov_vf(adev)) in sdma_v5_2_get_clockgating_state()
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| A D | mmhub_v1_7.c | 114 if (amdgpu_sriov_vf(adev)) in mmhub_v1_7_init_system_aperture_regs()
179 if (amdgpu_sriov_vf(adev)) in mmhub_v1_7_init_cache_regs()
243 if (amdgpu_sriov_vf(adev)) in mmhub_v1_7_disable_identity_aperture()
369 if (!amdgpu_sriov_vf(adev)) { in mmhub_v1_7_gart_disable()
388 if (amdgpu_sriov_vf(adev)) in mmhub_v1_7_set_fault_enable_default()
529 if (amdgpu_sriov_vf(adev)) in mmhub_v1_7_set_clockgating()
549 if (amdgpu_sriov_vf(adev)) in mmhub_v1_7_get_clockgating()
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