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Searched refs:bit_idx (Results 1 – 25 of 98) sorted by relevance

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/linux/drivers/clk/
A Dclk-gate.c70 reg = BIT(gate->bit_idx + 16); in clk_gate_endisable()
72 reg |= BIT(gate->bit_idx); in clk_gate_endisable()
77 reg |= BIT(gate->bit_idx); in clk_gate_endisable()
79 reg &= ~BIT(gate->bit_idx); in clk_gate_endisable()
111 reg ^= BIT(gate->bit_idx); in clk_gate_is_enabled()
113 reg &= BIT(gate->bit_idx); in clk_gate_is_enabled()
131 void __iomem *reg, u8 bit_idx, in __clk_hw_register_gate() argument
140 if (bit_idx > 15) { in __clk_hw_register_gate()
164 gate->bit_idx = bit_idx; in __clk_hw_register_gate()
186 void __iomem *reg, u8 bit_idx, in clk_register_gate() argument
[all …]
A Dclk-stm32f4.c49 u8 bit_idx; member
414 u8 bit_idx; member
478 am->bit_idx = bit_idx; in clk_register_apb_mul()
543 u8 bit_idx; member
815 pll->gate.bit_idx = vco->bit_idx; in stm32f4_rcc_register_pll()
985 rgate->gate.bit_idx = bit_idx; in clk_register_rgate()
1079 gate->bit_idx = bit_idx; in stm32_register_cclk()
1163 u8 bit_idx; member
1629 int offset_gate, u8 bit_idx, in stm32_register_aux_clk() argument
1646 gate->bit_idx = bit_idx; in stm32_register_aux_clk()
[all …]
A Dclk-stm32h7.c238 rgate->gate.bit_idx = bit_idx; in clk_register_ready_gate()
253 u8 bit_idx; member
342 gate->bit_idx = bit_idx; in _get_cgate()
593 u8 bit_idx; member
603 .bit_idx = _bit_idx,\
622 u8 bit_idx; member
637 .bit_idx = 24,
645 .bit_idx = 26,
653 .bit_idx = 28,
813 rgate->gate.bit_idx = cfg->bit_idx; in clk_register_stm32_pll()
[all …]
/linux/drivers/xen/events/
A Devents_2l.c170 int word_idx, bit_idx; in evtchn_2l_handle_events() local
180 bit_idx = evtchn % BITS_PER_LONG; in evtchn_2l_handle_events()
207 bit_idx = 0; in evtchn_2l_handle_events()
228 bit_idx = start_bit_idx; in evtchn_2l_handle_events()
235 bits = MASK_LSBS(pending_bits, bit_idx); in evtchn_2l_handle_events()
241 bit_idx = EVTCHN_FIRST_BIT(bits); in evtchn_2l_handle_events()
244 port = (word_idx * BITS_PER_EVTCHN_WORD) + bit_idx; in evtchn_2l_handle_events()
247 bit_idx = (bit_idx + 1) % BITS_PER_EVTCHN_WORD; in evtchn_2l_handle_events()
251 bit_idx ? word_idx : in evtchn_2l_handle_events()
253 __this_cpu_write(current_bit_idx, bit_idx); in evtchn_2l_handle_events()
[all …]
/linux/drivers/clk/imx/
A Dclk-gate2.c31 u8 bit_idx; member
47 reg &= ~(gate->cgr_mask << gate->bit_idx); in clk_gate2_do_shared_clks()
49 reg |= (gate->cgr_val & gate->cgr_mask) << gate->bit_idx; in clk_gate2_do_shared_clks()
89 static int clk_gate2_reg_is_enabled(void __iomem *reg, u8 bit_idx, in clk_gate2_reg_is_enabled() argument
94 if (((val >> bit_idx) & cgr_mask) == cgr_val) in clk_gate2_reg_is_enabled()
108 ret = clk_gate2_reg_is_enabled(gate->reg, gate->bit_idx, in clk_gate2_is_enabled()
138 void __iomem *reg, u8 bit_idx, u8 cgr_val, u8 cgr_mask, in clk_hw_register_gate2() argument
153 gate->bit_idx = bit_idx; in clk_hw_register_gate2()
A Dclk-lpcg-scu.c35 u8 bit_idx; member
53 reg &= ~(CLK_GATE_SCU_LPCG_MASK << clk->bit_idx); in clk_lpcg_scu_enable()
59 reg |= val << clk->bit_idx; in clk_lpcg_scu_enable()
76 reg &= ~(CLK_GATE_SCU_LPCG_MASK << clk->bit_idx); in clk_lpcg_scu_disable()
89 void __iomem *reg, u8 bit_idx, bool hw_gate) in __imx_clk_lpcg_scu() argument
101 clk->bit_idx = bit_idx; in __imx_clk_lpcg_scu()
A Dclk-scu.h43 void __iomem *reg, u8 bit_idx, bool hw_gate);
64 void __iomem *reg, u8 bit_idx, bool hw_gate) in imx_clk_lpcg_scu_dev() argument
67 bit_idx, hw_gate); in imx_clk_lpcg_scu_dev()
72 u8 bit_idx, bool hw_gate) in imx_clk_lpcg_scu() argument
75 bit_idx, hw_gate); in imx_clk_lpcg_scu()
/linux/drivers/clk/hisilicon/
A Dclkgate-separated.c27 u8 bit_idx; /* bits in enable/disable register */ member
41 reg = BIT(sclk->bit_idx); in clkgate_separated_enable()
58 reg = BIT(sclk->bit_idx); in clkgate_separated_disable()
72 reg &= BIT(sclk->bit_idx); in clkgate_separated_is_enabled()
86 void __iomem *reg, u8 bit_idx, in hisi_register_clkgate_sep() argument
104 sclk->bit_idx = bit_idx; in hisi_register_clkgate_sep()
/linux/drivers/clk/meson/
A Daxg.c338 .bit_idx = 27,
365 .bit_idx = 28,
403 .bit_idx = 29,
429 .bit_idx = 30,
457 .bit_idx = 31,
523 .bit_idx = 14,
681 .bit_idx = 0,
831 .bit_idx = 4,
846 .bit_idx = 3,
903 .bit_idx = 7,
[all …]
A Dmeson8b.c329 .bit_idx = 27,
357 .bit_idx = 28,
385 .bit_idx = 29,
413 .bit_idx = 30,
441 .bit_idx = 31,
506 .bit_idx = 14,
551 .bit_idx = 14,
596 .bit_idx = 14,
653 .bit_idx = 7,
835 .bit_idx = 8,
[all …]
A Dgxbb.c572 .bit_idx = 27,
599 .bit_idx = 28,
637 .bit_idx = 29,
663 .bit_idx = 30,
689 .bit_idx = 31,
895 .bit_idx = 7,
946 .bit_idx = 8,
1018 .bit_idx = 8,
1146 .bit_idx = 8,
1346 .bit_idx = 7,
[all …]
A Dg12a-aoclk.c48 .bit_idx = (_bit), \
80 .bit_idx = 14,
107 .bit_idx = 31,
180 .bit_idx = 30,
198 .bit_idx = 31,
271 .bit_idx = 30,
359 .bit_idx = 8,
A Dg12a.c220 .bit_idx = 24,
237 .bit_idx = 24,
293 .bit_idx = 24,
330 .bit_idx = 20,
1134 .bit_idx = 1,
1153 .bit_idx = 1,
1213 .bit_idx = 1,
2461 .bit_idx = 7,
2524 .bit_idx = 7,
2622 .bit_idx = 7,
[all …]
A Daxg-aoclk.c39 .bit_idx = (_bit), \
63 .bit_idx = 14,
78 .bit_idx = 31,
161 .bit_idx = 30,
249 .bit_idx = 8,
A Dclk-regmap.c18 return regmap_update_bits(clk->map, gate->offset, BIT(gate->bit_idx), in clk_regmap_gate_endisable()
19 set ? BIT(gate->bit_idx) : 0); in clk_regmap_gate_endisable()
40 val ^= BIT(gate->bit_idx); in clk_regmap_gate_is_enabled()
42 val &= BIT(gate->bit_idx); in clk_regmap_gate_is_enabled()
A Dgxbb-aoclk.c28 .bit_idx = (_bit), \
51 .bit_idx = 6,
66 .bit_idx = 31,
145 .bit_idx = 30,
A Dclk-regmap.h46 u8 bit_idx; member
121 .bit_idx = (_bit), \
/linux/drivers/clk/actions/
A Dowl-gate.c27 reg |= BIT(gate_hw->bit_idx); in owl_gate_set()
29 reg &= ~BIT(gate_hw->bit_idx); in owl_gate_set()
60 reg ^= BIT(gate_hw->bit_idx); in owl_gate_clk_is_enabled()
62 return !!(reg & BIT(gate_hw->bit_idx)); in owl_gate_clk_is_enabled()
A Dowl-gate.h18 u8 bit_idx; member
30 .bit_idx = _bit_idx, \
A Dowl-pll.c119 return !!(reg & BIT(pll_hw->bit_idx)); in owl_pll_is_enabled()
130 reg |= BIT(pll_hw->bit_idx); in owl_pll_set()
132 reg &= ~BIT(pll_hw->bit_idx); in owl_pll_set()
/linux/drivers/clk/mvebu/
A Dcp110-system-controller.c116 u8 bit_idx; member
126 BIT(gate->bit_idx), BIT(gate->bit_idx)); in cp110_gate_enable()
136 BIT(gate->bit_idx), 0); in cp110_gate_disable()
146 return val & BIT(gate->bit_idx); in cp110_gate_is_enabled()
157 struct regmap *regmap, u8 bit_idx) in cp110_register_gate() argument
176 gate->bit_idx = bit_idx; in cp110_register_gate()
/linux/arch/arm/mach-ep93xx/
A Dclock.c63 u8 bit_idx; member
79 return (val & BIT(psc->bit_idx)) ? 1 : 0; in ep93xx_clk_is_enabled()
92 val |= BIT(psc->bit_idx); in ep93xx_clk_enable()
112 val &= ~BIT(psc->bit_idx); in ep93xx_clk_disable()
129 u8 bit_idx) in ep93xx_clk_register_gate() argument
146 psc->bit_idx = bit_idx; in ep93xx_clk_register_gate()
324 u8 bit_idx) in clk_hw_register_ddiv() argument
341 psc->bit_idx = bit_idx; in clk_hw_register_ddiv()
444 psc->bit_idx = enable_bit; in clk_hw_register_div()
/linux/drivers/mmc/host/
A Dmeson-mx-sdhc-clkc.c117 clkc_data->mod_clk_en.bit_idx = 15; in meson_mx_sdhc_register_clkc()
125 clkc_data->tx_clk_en.bit_idx = 14; in meson_mx_sdhc_register_clkc()
133 clkc_data->rx_clk_en.bit_idx = 13; in meson_mx_sdhc_register_clkc()
141 clkc_data->sd_clk_en.bit_idx = 12; in meson_mx_sdhc_register_clkc()
/linux/drivers/clk/ralink/
A Dclk-mt7621.c55 u32 bit_idx; member
64 .bit_idx = _shift \
101 clk_gate->bit_idx, clk_gate->bit_idx); in mt7621_gate_enable()
109 regmap_update_bits(sysc, SYSC_REG_CLKCFG1, clk_gate->bit_idx, 0); in mt7621_gate_disable()
121 return val & BIT(clk_gate->bit_idx); in mt7621_gate_is_enabled()
/linux/drivers/clk/keystone/
A Dsyscon-clk.c22 u32 bit_idx; member
82 priv->idx = BIT(data->bit_idx); in ti_syscon_gate_clk_register()
139 .bit_idx = (_bit_idx), \

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