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Searched refs:clk_table (Results 1 – 25 of 27) sorted by relevance

12

/linux/drivers/clk/samsung/
A Dclk-s5pv210-audss.c69 struct clk_hw **clk_table; in s5pv210_audss_clk_probe() local
84 clk_table = clk_data->hws; in s5pv210_audss_clk_probe()
113 clk_table[CLK_MOUT_AUDSS] = clk_hw_register_mux(NULL, "mout_audss", in s5pv210_audss_clk_probe()
129 clk_table[CLK_DOUT_AUD_BUS] = clk_hw_register_divider(NULL, in s5pv210_audss_clk_probe()
132 clk_table[CLK_DOUT_I2S_A] = clk_hw_register_divider(NULL, in s5pv210_audss_clk_probe()
136 clk_table[CLK_I2S] = clk_hw_register_gate(NULL, "i2s_audss", in s5pv210_audss_clk_probe()
157 clk_table[CLK_HCLK_RP] = clk_hw_register_gate(NULL, "hclk_rp_audss", in s5pv210_audss_clk_probe()
162 if (IS_ERR(clk_table[i])) { in s5pv210_audss_clk_probe()
164 ret = PTR_ERR(clk_table[i]); in s5pv210_audss_clk_probe()
184 if (!IS_ERR(clk_table[i])) in s5pv210_audss_clk_probe()
[all …]
A Dclk-s3c2410-dclk.c245 struct clk_hw **clk_table; in s3c24xx_dclk_probe() local
255 clk_table = s3c24xx_dclk->clk_data.hws; in s3c24xx_dclk_probe()
305 if (IS_ERR(clk_table[i])) { in s3c24xx_dclk_probe()
307 ret = PTR_ERR(clk_table[i]); in s3c24xx_dclk_probe()
316 ret = clk_hw_register_clkdev(clk_table[MUX_CLKOUT0], in s3c24xx_dclk_probe()
345 clk_notifier_unregister(clk_table[DIV_DCLK0]->clk, in s3c24xx_dclk_probe()
349 if (clk_table[i] && !IS_ERR(clk_table[i])) in s3c24xx_dclk_probe()
350 clk_hw_unregister(clk_table[i]); in s3c24xx_dclk_probe()
361 clk_notifier_unregister(clk_table[DIV_DCLK1]->clk, in s3c24xx_dclk_remove()
363 clk_notifier_unregister(clk_table[DIV_DCLK0]->clk, in s3c24xx_dclk_remove()
[all …]
A Dclk-exynos-audss.c131 struct clk_hw **clk_table; in exynos_audss_clk_probe() local
153 clk_table = clk_data->hws; in exynos_audss_clk_probe()
195 clk_table[EXYNOS_MOUT_I2S] = clk_hw_register_mux(dev, "mout_i2s", in exynos_audss_clk_probe()
204 clk_table[EXYNOS_DOUT_AUD_BUS] = clk_hw_register_divider(dev, in exynos_audss_clk_probe()
212 clk_table[EXYNOS_SRP_CLK] = clk_hw_register_gate(dev, "srp_clk", in exynos_audss_clk_probe()
216 clk_table[EXYNOS_I2S_BUS] = clk_hw_register_gate(dev, "i2s_bus", in exynos_audss_clk_probe()
220 clk_table[EXYNOS_SCLK_I2S] = clk_hw_register_gate(dev, "sclk_i2s", in exynos_audss_clk_probe()
224 clk_table[EXYNOS_PCM_BUS] = clk_hw_register_gate(dev, "pcm_bus", in exynos_audss_clk_probe()
236 clk_table[EXYNOS_ADMA] = clk_hw_register_gate(dev, "adma", in exynos_audss_clk_probe()
242 if (IS_ERR(clk_table[i])) { in exynos_audss_clk_probe()
[all …]
/linux/drivers/clk/mmp/
A Dclk.c13 struct clk **clk_table; in mmp_clk_init() local
16 if (!clk_table) in mmp_clk_init()
19 unit->clk_table = clk_table; in mmp_clk_init()
21 unit->clk_data.clks = clk_table; in mmp_clk_init()
44 unit->clk_table[clks[i].id] = clk; in mmp_register_fixed_rate_clks()
66 unit->clk_table[clks[i].id] = clk; in mmp_register_fixed_factor_clks()
92 unit->clk_table[clks[i].id] = clk; in mmp_register_general_gate_clks()
120 unit->clk_table[clks[i].id] = clk; in mmp_register_gate_clks()
148 unit->clk_table[clks[i].id] = clk; in mmp_register_mux_clks()
175 unit->clk_table[clks[i].id] = clk; in mmp_register_div_clks()
[all …]
A Dclk-pll.c168 unit->clk_table[clks[i].id] = clk; in mmp_register_pll_clks()
/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
A Dvega10_processpptables.c577 clk_table = kzalloc(struct_size(clk_table, entries, clk_dep_table->ucNumEntries), in get_socclk_voltage_dependency_table()
579 if (!clk_table) in get_socclk_voltage_dependency_table()
638 *clk_table; in get_gfxclk_voltage_dependency_table() local
646 if (!clk_table) in get_gfxclk_voltage_dependency_table()
682 kfree(clk_table); in get_gfxclk_voltage_dependency_table()
701 *clk_table; in get_pix_clk_voltage_dependency_table() local
708 if (!clk_table) in get_pix_clk_voltage_dependency_table()
734 *clk_table; in get_dcefclk_voltage_dependency_table() local
759 clk_table = kzalloc(struct_size(clk_table, entries, num_entries), in get_dcefclk_voltage_dependency_table()
761 if (!clk_table) in get_dcefclk_voltage_dependency_table()
[all …]
/linux/drivers/gpu/drm/amd/pm/swsmu/smu13/
A Dyellow_carp_ppt.c720 *count = clk_table->NumSocClkLevelsEnabled; in yellow_carp_get_dpm_level_count()
723 *count = clk_table->VcnClkLevelsEnabled; in yellow_carp_get_dpm_level_count()
726 *count = clk_table->VcnClkLevelsEnabled; in yellow_carp_get_dpm_level_count()
729 *count = clk_table->NumDfPstatesEnabled; in yellow_carp_get_dpm_level_count()
732 *count = clk_table->NumDfPstatesEnabled; in yellow_carp_get_dpm_level_count()
748 if (!clk_table || clk_type >= SMU_CLK_COUNT) in yellow_carp_get_dpm_freq_by_index()
755 *freq = clk_table->SocClocks[dpm_level]; in yellow_carp_get_dpm_freq_by_index()
760 *freq = clk_table->VClocks[dpm_level]; in yellow_carp_get_dpm_freq_by_index()
765 *freq = clk_table->DClocks[dpm_level]; in yellow_carp_get_dpm_freq_by_index()
864 *max = clk_table->MaxGfxClk; in yellow_carp_get_dpm_ultimate_freq()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn301/
A Ddcn301_fpu.c251 struct clk_limit_table *clk_table = &bw_params->clk_table; in dcn301_update_bw_bounding_box() local
264 ASSERT(clk_table->num_entries); in dcn301_update_bw_bounding_box()
265 for (i = 0; i < clk_table->num_entries; i++) { in dcn301_update_bw_bounding_box()
275 clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; in dcn301_update_bw_bounding_box()
276 clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz; in dcn301_update_bw_bounding_box()
277 clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz; in dcn301_update_bw_bounding_box()
278 clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2; in dcn301_update_bw_bounding_box()
289 for (i = 0; i < clk_table->num_entries; i++) in dcn301_update_bw_bounding_box()
292 if (clk_table->num_entries) { in dcn301_update_bw_bounding_box()
293 dcn3_01_soc.num_states = clk_table->num_entries; in dcn301_update_bw_bounding_box()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/
A Ddcn30_clk_mgr.c185 &clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz, in dcn3_init_clocks()
190 &clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz, in dcn3_init_clocks()
195 &clk_mgr_base->bw_params->clk_table.entries[0].socclk_mhz, in dcn3_init_clocks()
201 &clk_mgr_base->bw_params->clk_table.entries[0].dispclk_mhz, in dcn3_init_clocks()
206 &clk_mgr_base->bw_params->clk_table.entries[0].dppclk_mhz, in dcn3_init_clocks()
211 &clk_mgr_base->bw_params->clk_table.entries[0].phyclk_mhz, in dcn3_init_clocks()
308 …clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].mem… in dcn3_update_clocks()
405 …clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].mem… in dcn3_set_hard_min_memclk()
408 clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz); in dcn3_set_hard_min_memclk()
421 …clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].mem… in dcn3_set_hard_max_memclk()
[all …]
/linux/drivers/clk/hisilicon/
A Dclk.c31 struct clk **clk_table; in hisi_clk_alloc() local
45 clk_table = devm_kmalloc_array(&pdev->dev, nr_clks, in hisi_clk_alloc()
46 sizeof(*clk_table), in hisi_clk_alloc()
48 if (!clk_table) in hisi_clk_alloc()
51 clk_data->clk_data.clks = clk_table; in hisi_clk_alloc()
62 struct clk **clk_table; in hisi_clk_init() local
76 clk_table = kcalloc(nr_clks, sizeof(*clk_table), GFP_KERNEL); in hisi_clk_init()
77 if (!clk_table) in hisi_clk_init()
80 clk_data->clk_data.clks = clk_table; in hisi_clk_init()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
A Ddcn31_clk_mgr.c326 .clk_table = {
433 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; in dcn31_build_watermark_ranges()
436 bw_params->clk_table.entries[i].dcfclk_mhz; in dcn31_build_watermark_ranges()
572 bw_params->clk_table.num_entries = j + 1; in dcn31_clk_mgr_helper_populate_bw_params()
583 for (i = 0; i < bw_params->clk_table.num_entries; i++, j--) { in dcn31_clk_mgr_helper_populate_bw_params()
589 bw_params->clk_table.entries[i].wck_ratio = 2; in dcn31_clk_mgr_helper_populate_bw_params()
592 bw_params->clk_table.entries[i].wck_ratio = 4; in dcn31_clk_mgr_helper_populate_bw_params()
595 bw_params->clk_table.entries[i].wck_ratio = 1; in dcn31_clk_mgr_helper_populate_bw_params()
599 bw_params->clk_table.entries[i].dispclk_mhz = max_dispclk; in dcn31_clk_mgr_helper_populate_bw_params()
600 bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk; in dcn31_clk_mgr_helper_populate_bw_params()
[all …]
/linux/drivers/gpu/drm/amd/pm/swsmu/smu11/
A Dvangogh_ppt.c545 *freq = clk_table->SocClocks[dpm_level]; in vangogh_get_dpm_clk_limited()
624 count = clk_table->NumSocClkLevelsEnabled; in vangogh_print_legacy_clk_levels()
628 count = clk_table->VcnClkLevelsEnabled; in vangogh_print_legacy_clk_levels()
632 count = clk_table->VcnClkLevelsEnabled; in vangogh_print_legacy_clk_levels()
636 count = clk_table->NumDfPstatesEnabled; in vangogh_print_legacy_clk_levels()
640 count = clk_table->NumDfPstatesEnabled; in vangogh_print_legacy_clk_levels()
726 count = clk_table->NumSocClkLevelsEnabled; in vangogh_print_clk_levels()
730 count = clk_table->VcnClkLevelsEnabled; in vangogh_print_clk_levels()
734 count = clk_table->VcnClkLevelsEnabled; in vangogh_print_clk_levels()
738 count = clk_table->NumDfPstatesEnabled; in vangogh_print_clk_levels()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/
A Drn_clk_mgr.c490 …ranges->reader_wm_sets[num_valid_sets].min_drain_clk_mhz = bw_params->clk_table.entries[i - 1].dcf… in build_watermark_ranges()
492 …ranges->reader_wm_sets[num_valid_sets].max_drain_clk_mhz = bw_params->clk_table.entries[i].dcfclk_… in build_watermark_ranges()
589 .clk_table = {
897 bw_params->clk_table.num_entries = j + 1; in rn_clk_mgr_helper_populate_bw_params()
899 for (i = 0; i < bw_params->clk_table.num_entries; i++, j--) { in rn_clk_mgr_helper_populate_bw_params()
900 bw_params->clk_table.entries[i].fclk_mhz = clock_table->FClocks[j].Freq; in rn_clk_mgr_helper_populate_bw_params()
901 bw_params->clk_table.entries[i].memclk_mhz = clock_table->MemClocks[j].Freq; in rn_clk_mgr_helper_populate_bw_params()
902 bw_params->clk_table.entries[i].voltage = clock_table->FClocks[j].Vol; in rn_clk_mgr_helper_populate_bw_params()
904 bw_params->clk_table.entries[i].socclk_mhz = find_socclk_for_voltage(clock_table, in rn_clk_mgr_helper_populate_bw_params()
905 bw_params->clk_table.entries[i].voltage); in rn_clk_mgr_helper_populate_bw_params()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dcn21/
A Ddcn21_resource.c1152 vlevel_max = bw_params->clk_table.num_entries - 1; in dcn21_calculate_wm()
1582 for (i = clk_table->num_entries; i > 1; i--) in construct_low_pstate_lvl()
1583 clk_table->entries[i] = clk_table->entries[i-1]; in construct_low_pstate_lvl()
1584 clk_table->entries[1] = clk_table->entries[0]; in construct_low_pstate_lvl()
1585 clk_table->num_entries++; in construct_low_pstate_lvl()
1593 struct clk_limit_table *clk_table = &bw_params->clk_table; in update_bw_bounding_box() local
1602 ASSERT(clk_table->num_entries); in update_bw_bounding_box()
1608 for (i = 0; i < clk_table->num_entries; i++) { in update_bw_bounding_box()
1637 for (i = 0; i < clk_table->num_entries + 1; i++) in update_bw_bounding_box()
1639 if (clk_table->num_entries) { in update_bw_bounding_box()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dcn302/
A Ddcn302_resource.c1306 if (bw_params->clk_table.entries[0].memclk_mhz) { in dcn302_update_bw_bounding_box()
1310 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz) in dcn302_update_bw_bounding_box()
1311 max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; in dcn302_update_bw_bounding_box()
1313 max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; in dcn302_update_bw_bounding_box()
1314 if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz) in dcn302_update_bw_bounding_box()
1315 max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; in dcn302_update_bw_bounding_box()
1317 max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; in dcn302_update_bw_bounding_box()
1344 num_uclk_states = bw_params->clk_table.num_entries; in dcn302_update_bw_bounding_box()
1360 bw_params->clk_table.entries[j].memclk_mhz * 16; in dcn302_update_bw_bounding_box()
1406 if (!bw_params->clk_table.entries[i].dtbclk_mhz && i > 0) in dcn302_update_bw_bounding_box()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dcn303/
A Ddcn303_resource.c1236 if (bw_params->clk_table.entries[0].memclk_mhz) { in dcn303_update_bw_bounding_box()
1240 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz) in dcn303_update_bw_bounding_box()
1241 max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; in dcn303_update_bw_bounding_box()
1243 max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; in dcn303_update_bw_bounding_box()
1245 max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; in dcn303_update_bw_bounding_box()
1247 max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; in dcn303_update_bw_bounding_box()
1272 num_uclk_states = bw_params->clk_table.num_entries; in dcn303_update_bw_bounding_box()
1287 bw_params->clk_table.entries[j].memclk_mhz * 16; in dcn303_update_bw_bounding_box()
1304 bw_params->clk_table.entries[j++].memclk_mhz * 16; in dcn303_update_bw_bounding_box()
1334 if (!bw_params->clk_table.entries[i].dtbclk_mhz && i > 0) in dcn303_update_bw_bounding_box()
[all …]
/linux/drivers/clk/axis/
A Dclk-artpec6.c20 struct clk *clk_table[ARTPEC6_CLK_NUMCLOCKS]; member
56 clks = clkdata->clk_table; in of_artpec6_clkctrl_setup()
107 clkdata->clk_data.clks = clkdata->clk_table; in of_artpec6_clkctrl_setup()
121 struct clk **clks = clkdata->clk_table; in artpec6_clkctrl_probe()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
A Dvg_clk_mgr.c421 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; in vg_build_watermark_ranges()
424 bw_params->clk_table.entries[i].dcfclk_mhz; in vg_build_watermark_ranges()
505 .clk_table = {
658 bw_params->clk_table.num_entries = j + 1; in vg_clk_mgr_helper_populate_bw_params()
660 for (i = 0; i < bw_params->clk_table.num_entries; i++, j--) { in vg_clk_mgr_helper_populate_bw_params()
661 bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].fclk; in vg_clk_mgr_helper_populate_bw_params()
662 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[j].memclk; in vg_clk_mgr_helper_populate_bw_params()
663 bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[j].voltage; in vg_clk_mgr_helper_populate_bw_params()
664 …bw_params->clk_table.entries[i].dcfclk_mhz = find_dcfclk_for_voltage(clock_table, clock_table->DfP… in vg_clk_mgr_helper_populate_bw_params()
673 if (i >= bw_params->clk_table.num_entries) { in vg_clk_mgr_helper_populate_bw_params()
/linux/drivers/acpi/pmic/
A Dtps68470_pmic.c168 static const struct tps68470_pmic_table clk_table[] = { variable
330 clk_table, in tps68470_pmic_clk_handler()
331 ARRAY_SIZE(clk_table)); in tps68470_pmic_clk_handler()
/linux/drivers/gpu/drm/amd/display/dc/dcn31/
A Ddcn31_resource.c2058 struct clk_limit_table *clk_table = &bw_params->clk_table; in dcn31_update_bw_bounding_box() local
2071 ASSERT(clk_table->num_entries); in dcn31_update_bw_bounding_box()
2074 for (i = 0; i < clk_table->num_entries; ++i) { in dcn31_update_bw_bounding_box()
2076 max_dispclk_mhz = clk_table->entries[i].dispclk_mhz; in dcn31_update_bw_bounding_box()
2077 if (clk_table->entries[i].dppclk_mhz > max_dppclk_mhz) in dcn31_update_bw_bounding_box()
2078 max_dppclk_mhz = clk_table->entries[i].dppclk_mhz; in dcn31_update_bw_bounding_box()
2081 for (i = 0; i < clk_table->num_entries; i++) { in dcn31_update_bw_bounding_box()
2096 …clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_… in dcn31_update_bw_bounding_box()
2111 for (i = 0; i < clk_table->num_entries; i++) in dcn31_update_bw_bounding_box()
2113 if (clk_table->num_entries) { in dcn31_update_bw_bounding_box()
[all …]
/linux/drivers/clk/rockchip/
A Dclk.c357 struct clk **clk_table; in rockchip_clk_init() local
364 clk_table = kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL); in rockchip_clk_init()
365 if (!clk_table) in rockchip_clk_init()
369 clk_table[i] = ERR_PTR(-ENOENT); in rockchip_clk_init()
372 ctx->clk_data.clks = clk_table; in rockchip_clk_init()
/linux/drivers/gpu/drm/amd/display/dc/dcn30/
A Ddcn30_resource.c2199 …min_dram_speed_mts = dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.n… in dcn30_calculate_wm_and_dlg_fp()
2406 if (bw_params->clk_table.entries[0].memclk_mhz) { in dcn30_update_bw_bounding_box()
2410 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz) in dcn30_update_bw_bounding_box()
2411 max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; in dcn30_update_bw_bounding_box()
2413 max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; in dcn30_update_bw_bounding_box()
2414 if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz) in dcn30_update_bw_bounding_box()
2415 max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; in dcn30_update_bw_bounding_box()
2416 if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz) in dcn30_update_bw_bounding_box()
2417 max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; in dcn30_update_bw_bounding_box()
2445 num_uclk_states = bw_params->clk_table.num_entries; in dcn30_update_bw_bounding_box()
[all …]
/linux/sound/soc/samsung/
A Di2s.c117 struct clk *clk_table[3]; member
808 rclksrc = priv->clk_table[CLK_I2S_RCLK_SRC]; in i2s_hw_params()
1250 if (!IS_ERR(priv->clk_table[i])) in i2s_unregister_clocks()
1251 clk_unregister(priv->clk_table[i]); in i2s_unregister_clocks()
1299 priv->clk_table[CLK_I2S_RCLK_SRC] = clk_register_mux(dev, in i2s_register_clock_provider()
1306 priv->clk_table[CLK_I2S_RCLK_PSR] = clk_register_divider(dev, in i2s_register_clock_provider()
1316 priv->clk_table[CLK_I2S_CDCLK] = clk_register_gate(dev, in i2s_register_clock_provider()
1323 priv->clk_data.clks = priv->clk_table; in i2s_register_clock_provider()
1527 priv->op_clk = clk_get_parent(priv->clk_table[CLK_I2S_RCLK_SRC]); in samsung_i2s_probe()
/linux/drivers/gpu/drm/amd/pm/swsmu/smu12/
A Drenoir_ppt.c196 DpmClocks_t *clk_table = smu->smu_table.clocks_table; in renoir_get_dpm_clk_limited() local
198 if (!clk_table || clk_type >= SMU_CLK_COUNT) in renoir_get_dpm_clk_limited()
205 *freq = clk_table->SocClocks[dpm_level].Freq; in renoir_get_dpm_clk_limited()
211 *freq = clk_table->FClocks[dpm_level].Freq; in renoir_get_dpm_clk_limited()
216 *freq = clk_table->DcfClocks[dpm_level].Freq; in renoir_get_dpm_clk_limited()
221 *freq = clk_table->FClocks[dpm_level].Freq; in renoir_get_dpm_clk_limited()
226 *freq = clk_table->VClocks[dpm_level].Freq; in renoir_get_dpm_clk_limited()
231 *freq = clk_table->DClocks[dpm_level].Freq; in renoir_get_dpm_clk_limited()
/linux/drivers/gpu/drm/amd/display/dc/inc/hw/
A Dclk_mgr.h214 struct clk_limit_table clk_table; member

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