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Searched refs:ctrl_base (Results 1 – 25 of 35) sorted by relevance

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/linux/arch/arm/mach-hisi/
A Dhotplug.c73 static void __iomem *ctrl_base; variable
125 ctrl_base + SCISOEN); in set_cpu_hi3620()
153 ctrl_base = of_iomap(node, 0); in hi3xxx_hotplug_init()
155 if (!ctrl_base) { in hi3xxx_hotplug_init()
166 if (!ctrl_base) { in hi3xxx_set_cpu()
183 ctrl_base = of_iomap(np, 0); in hix5hd2_hotplug_init()
185 if (!ctrl_base) in hix5hd2_hotplug_init()
195 if (!ctrl_base) in hix5hd2_set_cpu()
228 if (!ctrl_base) { in hip01_set_cpu()
231 ctrl_base = of_iomap(np, 0); in hip01_set_cpu()
[all …]
A Dplatsmp.c21 static void __iomem *ctrl_base; variable
26 if (!cpu || !ctrl_base) in hi3xxx_set_cpu_jump()
34 if (!cpu || !ctrl_base) in hi3xxx_get_cpu_jump()
36 return readl_relaxed(ctrl_base + ((cpu - 1) << 2)); in hi3xxx_get_cpu_jump()
62 if (!ctrl_base) { in hi3xxx_smp_prepare_cpus()
68 ctrl_base = of_iomap(np, 0); in hi3xxx_smp_prepare_cpus()
69 if (!ctrl_base) { in hi3xxx_smp_prepare_cpus()
77 ctrl_base += offset; in hi3xxx_smp_prepare_cpus()
162 ctrl_base = of_iomap(node, 0); in hip01_boot_secondary()
165 remap_reg_value = readl_relaxed(ctrl_base + REG_SC_CTRL); in hip01_boot_secondary()
[all …]
/linux/drivers/phy/broadcom/
A Dphy-brcm-usb-init.c422 brcm_usb_writel(data, USB_CTRL_REG(ctrl_base, MDIO)); in brcmusb_usb_mdio_read()
424 brcm_usb_writel(data, USB_CTRL_REG(ctrl_base, MDIO)); in brcmusb_usb_mdio_read()
428 brcm_usb_writel(data, USB_CTRL_REG(ctrl_base, MDIO)); in brcmusb_usb_mdio_read()
461 USB_CTRL_UNSET(ctrl_base, PLL_CTL, PLL_RESETB); in brcmusb_usb_phy_ldo_fix()
464 USB_CTRL_SET(ctrl_base, PLL_CTL, PLL_RESETB); in brcmusb_usb_phy_ldo_fix()
630 brcmusb_usb3_pll_fix(ctrl_base); in brcmusb_usb3_phy_workarounds()
632 brcmusb_usb3_ssc_enable(ctrl_base); in brcmusb_usb3_phy_workarounds()
633 brcmusb_usb3_enable_pipe_reset(ctrl_base); in brcmusb_usb3_phy_workarounds()
634 brcmusb_usb3_enable_sigdet(ctrl_base); in brcmusb_usb3_phy_workarounds()
635 brcmusb_usb3_enable_skip_align(ctrl_base); in brcmusb_usb3_phy_workarounds()
[all …]
A Dphy-brcm-sata.c74 void __iomem *ctrl_base; member
208 return priv->ctrl_base + (port->portnum * size); in brcm_sata_ctrl_base()
431 void __iomem *ctrl_base = brcm_sata_ctrl_base(port); in brcm_ns2_sata_init() local
462 writel(PHY_CTRL_1_RESET, ctrl_base + PHY_CTRL_1); in brcm_ns2_sata_init()
464 writel(0x0, ctrl_base + PHY_CTRL_1); in brcm_ns2_sata_init()
780 priv->ctrl_base = devm_platform_ioremap_resource_byname(pdev, "phy-ctrl"); in brcm_sata_phy_probe()
781 if (IS_ERR(priv->ctrl_base)) in brcm_sata_phy_probe()
782 return PTR_ERR(priv->ctrl_base); in brcm_sata_phy_probe()
/linux/drivers/fsi/
A Dfsi-master-aspeed.c34 static const u32 ctrl_base = 0x80000000; variable
242 ret = opb_writel(aspeed, ctrl_base + FSI_MRESP0, in check_errors()
401 opb_writel(aspeed, ctrl_base + FSI_MRESP0, reg); in aspeed_master_init()
406 opb_writel(aspeed, ctrl_base + FSI_MRESP0, reg); in aspeed_master_init()
409 opb_writel(aspeed, ctrl_base + FSI_MECTRL, reg); in aspeed_master_init()
417 opb_writel(aspeed, ctrl_base + FSI_MMODE, reg); in aspeed_master_init()
420 opb_writel(aspeed, ctrl_base + FSI_MDLYR, reg); in aspeed_master_init()
423 opb_writel(aspeed, ctrl_base + FSI_MSENP0, reg); in aspeed_master_init()
428 opb_writel(aspeed, ctrl_base + FSI_MCENP0, reg); in aspeed_master_init()
430 opb_readl(aspeed, ctrl_base + FSI_MAEB, NULL); in aspeed_master_init()
[all …]
/linux/drivers/video/fbdev/riva/
A Dnv_driver.c319 (volatile U032 __iomem *)(par->ctrl_base + 0x00680000); in riva_common_setup()
321 (volatile U032 __iomem *)(par->ctrl_base + 0x00100000); in riva_common_setup()
323 (volatile U032 __iomem *)(par->ctrl_base + 0x00002000); in riva_common_setup()
325 (volatile U032 __iomem *)(par->ctrl_base + 0x00400000); in riva_common_setup()
327 (volatile U032 __iomem *)(par->ctrl_base + 0x00101000); in riva_common_setup()
329 (volatile U032 __iomem *)(par->ctrl_base + 0x00009000); in riva_common_setup()
331 (volatile U032 __iomem *)(par->ctrl_base + 0x00000000); in riva_common_setup()
333 (volatile U032 __iomem *)(par->ctrl_base + 0x00800000); in riva_common_setup()
334 par->riva.PCIO0 = par->ctrl_base + 0x00601000; in riva_common_setup()
335 par->riva.PDIO0 = par->ctrl_base + 0x00681000; in riva_common_setup()
[all …]
/linux/drivers/staging/media/hantro/
A Dimx8m_vpu_hw.c33 val = readl(vpu->ctrl_base + CTRL_SOFT_RESET); in imx8m_soft_reset()
35 writel(val, vpu->ctrl_base + CTRL_SOFT_RESET); in imx8m_soft_reset()
40 val = readl(vpu->ctrl_base + CTRL_SOFT_RESET); in imx8m_soft_reset()
42 writel(val, vpu->ctrl_base + CTRL_SOFT_RESET); in imx8m_soft_reset()
49 val = readl(vpu->ctrl_base + CTRL_CLOCK_ENABLE); in imx8m_clk_enable()
51 writel(val, vpu->ctrl_base + CTRL_CLOCK_ENABLE); in imx8m_clk_enable()
68 writel(0xffffffff, vpu->ctrl_base + CTRL_G1_DEC_FUSE); in imx8mq_runtime_resume()
69 writel(0xffffffff, vpu->ctrl_base + CTRL_G1_PP_FUSE); in imx8mq_runtime_resume()
70 writel(0xffffffff, vpu->ctrl_base + CTRL_G2_DEC_FUSE); in imx8mq_runtime_resume()
192 vpu->ctrl_base = vpu->reg_bases[vpu->variant->num_regs - 1]; in imx8mq_vpu_hw_init()
/linux/arch/mips/pci/
A Dpci-ar724x.c41 void __iomem *ctrl_base; member
60 reset = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_RESET); in ar724x_pci_check_link()
236 base = apc->ctrl_base; in ar724x_pci_irq_handler()
256 base = apc->ctrl_base; in ar724x_pci_irq_unmask()
277 base = apc->ctrl_base; in ar724x_pci_irq_mask()
311 base = apc->ctrl_base; in ar724x_pci_irq_init()
349 app = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_APP); in ar724x_pci_hw_init()
351 __raw_writel(app, apc->ctrl_base + AR724X_PCI_REG_APP); in ar724x_pci_hw_init()
375 apc->ctrl_base = devm_platform_ioremap_resource_byname(pdev, "ctrl_base"); in ar724x_pci_probe()
376 if (IS_ERR(apc->ctrl_base)) in ar724x_pci_probe()
[all …]
/linux/arch/arm/mach-omap2/
A Domap_phy_internal.c36 void __iomem *ctrl_base; in omap4430_phy_power_down() local
41 ctrl_base = ioremap(OMAP443X_SCM_BASE, SZ_1K); in omap4430_phy_power_down()
42 if (!ctrl_base) { in omap4430_phy_power_down()
48 writel_relaxed(PHY_PD, ctrl_base + CONTROL_DEV_CONF); in omap4430_phy_power_down()
50 iounmap(ctrl_base); in omap4430_phy_power_down()
/linux/arch/arm/mm/
A Dcache-uniphier.c73 void __iomem *ctrl_base; member
224 writel_relaxed(val, data->ctrl_base + UNIPHIER_SSCC); in __uniphier_cache_enable()
374 data->ctrl_base = of_iomap(np, 0); in __uniphier_cache_init()
375 if (!data->ctrl_base) { in __uniphier_cache_init()
395 data->way_ctrl_base = data->ctrl_base + 0xc00; in __uniphier_cache_init()
412 data->way_ctrl_base = data->ctrl_base + 0x870; in __uniphier_cache_init()
416 data->way_ctrl_base = data->ctrl_base + 0x840; in __uniphier_cache_init()
445 iounmap(data->ctrl_base); in __uniphier_cache_init()
/linux/drivers/usb/musb/
A Dmusb_dsps.c173 void __iomem *reg_base = musb->ctrl_base; in dsps_musb_enable()
199 void __iomem *reg_base = musb->ctrl_base; in dsps_musb_disable()
317 void __iomem *reg_base = musb->ctrl_base; in dsps_interrupt()
419 glue->regset.base = musb->ctrl_base; in dsps_musb_dbg_init()
440 musb->ctrl_base = reg_base; in dsps_musb_init()
515 void __iomem *ctrl_base = musb->ctrl_base; in dsps_musb_set_mode() local
518 reg = musb_readl(ctrl_base, wrp->mode); in dsps_musb_set_mode()
531 musb_writel(ctrl_base, wrp->mode, reg); in dsps_musb_set_mode()
544 musb_writel(ctrl_base, wrp->mode, reg); in dsps_musb_set_mode()
988 mbase = musb->ctrl_base; in dsps_suspend()
[all …]
A Ddavinci.c83 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp); in davinci_musb_enable()
87 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp); in davinci_musb_enable()
92 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp); in davinci_musb_enable()
101 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_SET_REG, in davinci_musb_enable()
115 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_CLR_REG, in davinci_musb_disable()
119 musb_writel(musb->ctrl_base, DAVINCI_USB_EOI_REG, 0); in davinci_musb_disable()
213 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_SET_REG, in otg_timer()
249 void __iomem *tibase = musb->ctrl_base; in davinci_musb_interrupt()
359 void __iomem *tibase = musb->ctrl_base; in davinci_musb_init()
A Dtusb6010.c46 void __iomem *tbase = musb->ctrl_base; in tusb_get_revision()
63 void __iomem *tbase = musb->ctrl_base; in tusb_print_revision()
96 void __iomem *tbase = musb->ctrl_base; in tusb_wbus_quirk()
328 void __iomem *tbase = musb->ctrl_base; in tusb_draw_power()
364 void __iomem *tbase = musb->ctrl_base; in tusb_set_clock_source()
391 void __iomem *tbase = musb->ctrl_base; in tusb_allow_idle()
428 void __iomem *tbase = musb->ctrl_base; in tusb_musb_vbus_status()
553 void __iomem *tbase = musb->ctrl_base; in tusb_musb_set_vbus()
630 void __iomem *tbase = musb->ctrl_base; in tusb_musb_set_mode()
822 void __iomem *tbase = musb->ctrl_base; in tusb_musb_interrupt()
[all …]
A Dmusb_cppi41.c359 musb_writel(musb->ctrl_base, USB_CTRL_TX_MODE, new_mode); in cppi41_set_dma_mode()
362 musb_writel(musb->ctrl_base, USB_CTRL_RX_MODE, new_mode); in cppi41_set_dma_mode()
388 musb_writel(musb->ctrl_base, DA8XX_USB_MODE, new_mode); in da8xx_set_dma_mode()
407 musb_writel(controller->controller.musb->ctrl_base, in cppi41_set_autoreq_mode()
439 musb_writel(musb->ctrl_base, in cppi41_configure_channel()
449 musb_writel(musb->ctrl_base, in cppi41_configure_channel()
626 musb_writel(musb->ctrl_base, controller->tdown_reg, in cppi41_dma_channel_abort()
632 musb_writel(musb->ctrl_base, controller->tdown_reg, tdbit); in cppi41_dma_channel_abort()
A Dda8xx.c86 void __iomem *reg_base = musb->ctrl_base; in da8xx_musb_enable()
105 void __iomem *reg_base = musb->ctrl_base; in da8xx_musb_disable()
164 musb_writel(musb->ctrl_base, DA8XX_USB_INTR_SRC_SET_REG, in otg_timer()
225 void __iomem *reg_base = musb->ctrl_base; in da8xx_musb_interrupt()
357 void __iomem *reg_base = musb->ctrl_base; in da8xx_musb_init()
448 void __iomem *reg_base = musb->ctrl_base; in da8xx_dma_controller_callback()
A Dam35x.c83 void __iomem *reg_base = musb->ctrl_base; in am35x_musb_enable()
103 void __iomem *reg_base = musb->ctrl_base; in am35x_musb_disable()
152 musb_writel(musb->ctrl_base, CORE_INTR_SRC_SET_REG, in otg_timer()
200 void __iomem *reg_base = musb->ctrl_base; in am35x_musb_interrupt()
333 void __iomem *reg_base = musb->ctrl_base; in am35x_musb_init()
A Dtusb6010_omap.c585 void __iomem *tbase = musb->ctrl_base; in tusb_dma_controller_create()
591 musb_writel(musb->ctrl_base, TUSB_DMA_INT_MASK, 0x7fffffff); in tusb_dma_controller_create()
592 musb_writel(musb->ctrl_base, TUSB_DMA_EP_MAP, 0); in tusb_dma_controller_create()
604 tusb_dma->tbase = musb->ctrl_base; in tusb_dma_controller_create()
/linux/drivers/leds/
A Dleds-sc27xx-bltc.c90 u32 ctrl_base = leds->priv->base + SC27XX_LEDS_CTRL; in sc27xx_led_enable() local
102 return regmap_update_bits(regmap, ctrl_base, in sc27xx_led_enable()
110 u32 ctrl_base = leds->priv->base + SC27XX_LEDS_CTRL; in sc27xx_led_disable() local
113 return regmap_update_bits(regmap, ctrl_base, in sc27xx_led_disable()
151 u32 ctrl_base = leds->priv->base + SC27XX_LEDS_CTRL; in sc27xx_led_pattern_clear() local
161 err = regmap_update_bits(regmap, ctrl_base, in sc27xx_led_pattern_clear()
177 u32 ctrl_base = leds->priv->base + SC27XX_LEDS_CTRL; in sc27xx_led_pattern_set() local
229 err = regmap_update_bits(regmap, ctrl_base, in sc27xx_led_pattern_set()
/linux/sound/pci/
A Dsis7019.c83 void __iomem *ctrl_base; member
193 void __iomem *base = voice->ctrl_base; in sis_update_sso()
505 void __iomem *ctrl_base = voice->ctrl_base; in sis_pcm_playback_prepare() local
546 writel(format, ctrl_base + SIS_PLAY_DMA_FORMAT_CSO); in sis_pcm_playback_prepare()
547 writel(dma_addr, ctrl_base + SIS_PLAY_DMA_BASE); in sis_pcm_playback_prepare()
548 writel(control, ctrl_base + SIS_PLAY_DMA_CONTROL); in sis_pcm_playback_prepare()
549 writel(sso_eso, ctrl_base + SIS_PLAY_DMA_SSO_ESO); in sis_pcm_playback_prepare()
562 readl(ctrl_base); in sis_pcm_playback_prepare()
703 void __iomem *play_base = timing->ctrl_base; in sis_prepare_timing_voice()
756 timing->sync_base = voice->ctrl_base; in sis_prepare_timing_voice()
[all …]
/linux/drivers/spi/
A Dspi-ti-qspi.c48 struct regmap *ctrl_base; member
533 if (qspi->ctrl_base) { in ti_qspi_enable_memory_map()
534 regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg, in ti_qspi_enable_memory_map()
547 if (qspi->ctrl_base) in ti_qspi_disable_memory_map()
548 regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg, in ti_qspi_disable_memory_map()
826 qspi->ctrl_base = in ti_qspi_probe()
829 if (IS_ERR(qspi->ctrl_base)) { in ti_qspi_probe()
830 ret = PTR_ERR(qspi->ctrl_base); in ti_qspi_probe()
/linux/drivers/dma/
A Ddma-jz4780.c150 void __iomem *ctrl_base; member
197 return readl(jzdma->ctrl_base + reg); in jz4780_dma_ctrl_readl()
203 writel(val, jzdma->ctrl_base + reg); in jz4780_dma_ctrl_writel()
868 jzdma->ctrl_base = devm_ioremap_resource(dev, res); in jz4780_dma_probe()
869 if (IS_ERR(jzdma->ctrl_base)) in jz4780_dma_probe()
870 return PTR_ERR(jzdma->ctrl_base); in jz4780_dma_probe()
877 jzdma->ctrl_base = jzdma->chn_base + JZ4780_DMA_CTRL_OFFSET; in jz4780_dma_probe()
/linux/drivers/clk/samsung/
A Dclk-cpu.c369 base = cpuclk->ctrl_base; in exynos_cpuclk_notifier_cb()
392 base = cpuclk->ctrl_base; in exynos5433_cpuclk_notifier_cb()
433 cpuclk->ctrl_base = ctx->reg_base + offset; in exynos_register_cpu_clock()
A Dclk-cpu.h50 void __iomem *ctrl_base; member
/linux/arch/arm/kernel/
A Dhw_breakpoint.c329 int i, max_slots, ctrl_base, val_base; in arch_install_hw_breakpoint() local
337 ctrl_base = ARM_BASE_BCR; in arch_install_hw_breakpoint()
343 ctrl_base = ARM_BASE_WCR; in arch_install_hw_breakpoint()
369 ctrl_base = ARM_BASE_BCR + core_num_brps; in arch_install_hw_breakpoint()
378 write_wb_reg(ctrl_base + i, ctrl); in arch_install_hw_breakpoint()
/linux/drivers/perf/
A Darm-cci.c101 void __iomem *ctrl_base; member
375 rev = readl_relaxed(cci_pmu->ctrl_base + CCI_PID2) & CCI_PID2_REV_MASK; in probe_cci400_revision()
673 val = readl_relaxed(cci_pmu->ctrl_base + CCI_PMCR) | CCI_PMCR_CEN; in __cci_pmu_enable_nosync()
674 writel(val, cci_pmu->ctrl_base + CCI_PMCR); in __cci_pmu_enable_nosync()
690 val = readl_relaxed(cci_pmu->ctrl_base + CCI_PMCR) & ~CCI_PMCR_CEN; in __cci_pmu_disable()
691 writel(val, cci_pmu->ctrl_base + CCI_PMCR); in __cci_pmu_disable()
795 return (readl_relaxed(cci_pmu->ctrl_base + CCI_PMCR) & in pmu_get_max_counters()
1608 cci_pmu->ctrl_base = *(void __iomem **)dev->platform_data; in cci_pmu_alloc()

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