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Searched refs:ddr (Results 1 – 25 of 259) sorted by relevance

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/linux/Documentation/devicetree/bindings/perf/
A Dfsl-imx-ddr.yaml16 - fsl,imx8-ddr-pmu
17 - fsl,imx8m-ddr-pmu
18 - fsl,imx8mq-ddr-pmu
19 - fsl,imx8mm-ddr-pmu
20 - fsl,imx8mn-ddr-pmu
21 - fsl,imx8mp-ddr-pmu
24 - fsl,imx8mm-ddr-pmu
25 - fsl,imx8mn-ddr-pmu
26 - fsl,imx8mq-ddr-pmu
27 - fsl,imx8mp-ddr-pmu
[all …]
/linux/Documentation/devicetree/bindings/memory-controllers/
A Dqca,ath79-ddr-controller.yaml22 - const: qca,ar9132-ddr-controller
23 - const: qca,ar7240-ddr-controller
26 - qca,ar7100-ddr-controller
27 - qca,ar7240-ddr-controller
29 "#qca,ddr-wb-channel-cells":
41 - "#qca,ddr-wb-channel-cells"
49 compatible = "qca,ar9132-ddr-controller",
50 "qca,ar7240-ddr-controller";
53 #qca,ddr-wb-channel-cells = <1>;
58 qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
[all …]
A Dcalxeda-ddr-ctrlr.yaml4 $id: http://devicetree.org/schemas/memory-controllers/calxeda-ddr-ctrlr.yaml#
20 - calxeda,hb-ddr-ctrl
21 - calxeda,ecx-2000-ddr-ctrl
39 compatible = "calxeda,hb-ddr-ctrl";
A Dti,da8xx-ddrctl.yaml19 const: ti,da850-ddr-controller
33 compatible = "ti,da850-ddr-controller";
/linux/Documentation/devicetree/bindings/arm/bcm/
A Dbrcm,brcmstb.txt169 "brcm,brcmstb-ddr-phy-v71.1"
170 "brcm,brcmstb-ddr-phy-v72.0"
171 "brcm,brcmstb-ddr-phy-v225.1"
172 "brcm,brcmstb-ddr-phy-v240.1"
197 "brcm,brcmstb-memc-ddr"
210 ddr-phy@f1106000 {
220 memc-ddr@f1102000 {
230 ddr-phy@f1186000 {
240 memc-ddr@f1182000 {
250 ddr-phy@f1206000 {
[all …]
/linux/Documentation/devicetree/bindings/interrupt-controller/
A Dqca,ath79-cpu-intc.txt5 qca,ddr-wb-channels and qca,ddr-wb-channel-interrupts properties.
20 - qca,ddr-wb-channel-interrupts: List of the interrupts needing a write
22 - qca,ddr-wb-channels: List of phandles to the write buffer channels for
23 each interrupt. If qca,ddr-wb-channel-interrupts is not present the interrupt
34 qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
35 qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
43 #qca,ddr-wb-channel-cells = <1>;
/linux/Documentation/devicetree/bindings/mips/brcm/
A Dsoc.txt75 memc-ddr@2000 {
79 ddr-phy@6000 {
92 "brcm,brcmstb-ddr-phy-v64.5"
93 "brcm,brcmstb-ddr-phy"
99 ddr-phy@6000 {
110 "brcm,bcm7425-memc-ddr"
111 "brcm,bcm7429-memc-ddr"
112 "brcm,bcm7435-memc-ddr" and
113 "brcm,brcmstb-memc-ddr"
119 memc-ddr@2000 {
[all …]
/linux/arch/arm/boot/dts/
A Dbcm7445.dtsi239 memc-ddr@2000 {
240 compatible = "brcm,brcmstb-memc-ddr";
244 ddr-phy@6000 {
245 compatible = "brcm,brcmstb-ddr-phy-v240.1";
261 memc-ddr@2000 {
262 compatible = "brcm,brcmstb-memc-ddr";
266 ddr-phy@6000 {
267 compatible = "brcm,brcmstb-ddr-phy-v240.1";
283 memc-ddr@2000 {
284 compatible = "brcm,brcmstb-memc-ddr";
[all …]
/linux/include/memory/
A Drenesas-rpc-if.h26 bool ddr; member
32 bool ddr; member
44 bool ddr; member
52 bool ddr; member
77 u32 ddr; /* DRDRENR or SMDRENR */ member
/linux/arch/mips/rb532/
A Dprom.c103 struct ddr_ram __iomem *ddr; in prom_init() local
107 ddr = ioremap(ddr_reg[0].start, in prom_init()
110 if (!ddr) { in prom_init()
115 ddrbase = (phys_addr_t)&ddr->ddrbase; in prom_init()
116 memsize = (phys_addr_t)&ddr->ddrmask; in prom_init()
/linux/Documentation/devicetree/bindings/clock/
A Damlogic,meson8-ddr-clkc.yaml4 $id: http://devicetree.org/schemas/clock/amlogic,meson8-ddr-clkc.yaml#
15 - amlogic,meson8-ddr-clkc
16 - amlogic,meson8b-ddr-clkc
43 compatible = "amlogic,meson8-ddr-clkc";
/linux/arch/mips/boot/dts/qca/
A Dar9132.dtsi28 qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
29 qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
52 compatible = "qca,ar9132-ddr-controller",
53 "qca,ar7240-ddr-controller";
56 #qca,ddr-wb-channel-cells = <1>;
98 clock-output-names = "cpu", "ddr", "ahb";
A Dar9331.dtsi28 qca,ddr-wb-channel-interrupts = <2>, <3>;
29 qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>;
56 compatible = "qca,ar7240-ddr-controller";
59 #qca,ddr-wb-channel-cells = <1>;
/linux/drivers/media/pci/cx18/
A Dcx18-cards.c74 .ddr = {
121 .ddr = {
168 .ddr = {
221 .ddr = {
274 .ddr = {
334 .ddr = {
390 .ddr = {
439 .ddr = {
487 .ddr = {
540 .ddr = {
A Dcx18-firmware.c324 cx18_write_reg(cx, cx->card->ddr.chip_config, CX18_DDR_CHIP_CONFIG); in cx18_init_memory()
328 cx18_write_reg(cx, cx->card->ddr.refresh, CX18_DDR_REFRESH); in cx18_init_memory()
329 cx18_write_reg(cx, cx->card->ddr.timing1, CX18_DDR_TIMING1); in cx18_init_memory()
330 cx18_write_reg(cx, cx->card->ddr.timing2, CX18_DDR_TIMING2); in cx18_init_memory()
335 cx18_write_reg(cx, cx->card->ddr.tune_lane, CX18_DDR_TUNE_LANE); in cx18_init_memory()
336 cx18_write_reg(cx, cx->card->ddr.initial_emrs, CX18_DDR_INITIAL_EMRS); in cx18_init_memory()
/linux/drivers/memory/
A Drenesas-rpc-if.c334 rpc->ddr = 0; in rpcif_prepare()
341 if (op->cmd.ddr) in rpcif_prepare()
342 rpc->ddr = RPCIF_SMDRENR_HYPE(0x5); in rpcif_prepare()
358 if (op->addr.ddr) in rpcif_prepare()
359 rpc->ddr |= RPCIF_SMDRENR_ADDRE; in rpcif_prepare()
377 if (op->option.ddr) in rpcif_prepare()
378 rpc->ddr |= RPCIF_SMDRENR_OPDRE; in rpcif_prepare()
397 if (op->data.ddr) in rpcif_prepare()
398 rpc->ddr |= RPCIF_SMDRENR_SPIDRE; in rpcif_prepare()
425 regmap_write(rpc->regmap, RPCIF_SMDRENR, rpc->ddr); in rpcif_manual_xfer()
[all …]
/linux/drivers/mtd/hyperbus/
A Drpc-if.c29 .ddr = true,
33 .ddr = true,
38 .ddr = true,
42 .ddr = true,
/linux/sound/soc/intel/atom/sst/
A Dsst_pci.c53 ctx->ddr = pcim_iomap(pci, 0, in sst_platform_get_resources()
55 if (!ctx->ddr) { in sst_platform_get_resources()
59 dev_dbg(ctx->dev, "sst: DDR Ptr %p\n", ctx->ddr); in sst_platform_get_resources()
61 ctx->ddr = NULL; in sst_platform_get_resources()
A Dsst.c480 fw_save->ddr = kvzalloc(ctx->ddr_end - ctx->ddr_base, GFP_KERNEL); in intel_sst_suspend()
481 if (!fw_save->ddr) { in intel_sst_suspend()
483 goto ddr; in intel_sst_suspend()
489 memcpy32_fromio(fw_save->ddr, ctx->ddr, ctx->ddr_end - ctx->ddr_base); in intel_sst_suspend()
494 ddr: in intel_sst_suspend()
525 memcpy32_toio(ctx->ddr, fw_save->ddr, ctx->ddr_end - ctx->ddr_base); in intel_sst_resume()
530 kvfree(fw_save->ddr); in intel_sst_resume()
/linux/arch/mips/boot/dts/brcm/
A Dbcm7425.dtsi544 memc-ddr@2000 {
545 compatible = "brcm,brcmstb-memc-ddr";
549 ddr-phy@6000 {
550 compatible = "brcm,brcmstb-ddr-phy";
555 compatible = "brcm,brcmstb-ddr-shimphy";
571 memc-ddr@2000 {
572 compatible = "brcm,brcmstb-memc-ddr";
576 ddr-phy@6000 {
577 compatible = "brcm,brcmstb-ddr-phy";
582 compatible = "brcm,brcmstb-ddr-shimphy";
A Dbcm7435.dtsi559 memc-ddr@2000 {
560 compatible = "brcm,brcmstb-memc-ddr";
564 ddr-phy@6000 {
565 compatible = "brcm,brcmstb-ddr-phy";
570 compatible = "brcm,brcmstb-ddr-shimphy";
586 memc-ddr@2000 {
587 compatible = "brcm,brcmstb-memc-ddr";
591 ddr-phy@6000 {
592 compatible = "brcm,brcmstb-ddr-phy";
597 compatible = "brcm,brcmstb-ddr-shimphy";
/linux/Documentation/devicetree/bindings/mmc/
A Dsdhci-msm.txt56 - qcom,ddr-config: Certain chipsets and platforms require particular settings
70 1. Data path : sdhc to ddr
73 is "sdhc-ddr" and for config interconnect path it is
97 interconnect-names = "sdhc-ddr","cpu-sdhc";
100 qcom,ddr-config = <0x80040868>;
120 qcom,ddr-config = <0x80040868>;
/linux/arch/arm64/boot/dts/freescale/
A Dimx8-ss-ddr.dtsi13 ddr-pmu@5c020000 {
14 compatible = "fsl,imx8-ddr-pmu";
/linux/Documentation/devicetree/bindings/mfd/
A Drohm,bd9576-pmic.yaml47 rohm,ddr-sel-low:
50 the ddr-sel pin low or high. Set this property if ddr-sel is grounded.
97 rohm,ddr-sel-low;
/linux/drivers/mmc/host/
A Dmeson-gx-mmc.c159 bool ddr; member
350 bool ddr) in meson_mmc_clk_set() argument
357 if (host->ddr == ddr && host->req_rate == rate) in meson_mmc_clk_set()
374 if (ddr) { in meson_mmc_clk_set()
382 host->ddr = ddr; in meson_mmc_clk_set()
395 if (ddr) { in meson_mmc_clk_set()
559 bool ddr; in meson_mmc_prepare_ios_clock() local
564 ddr = true; in meson_mmc_prepare_ios_clock()
568 ddr = false; in meson_mmc_prepare_ios_clock()
572 return meson_mmc_clk_set(host, ios->clock, ddr); in meson_mmc_prepare_ios_clock()

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