Searched refs:div4 (Results 1 – 4 of 4) sorted by relevance
43 - clock-names: shall be "pll0_sysclk3", "div4.5"71 div4p5_clk: div4.5 {81 clock-names = "pll0_sysclk3", "div4.5";
122 #define UNIPHIER_CLK_DIV5(parent, div0, div1, div2, div3, div4) \ argument124 UNIPHIER_CLK_DIV(parent, div4)
400 div4p5_clk: div4.5 {410 clock-names = "pll0_sysclk3", "div4.5";
551 #define div4(v) ((v)>>2) macro
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