| /linux/drivers/clk/rockchip/ |
| A D | clk.h | 452 u8 div_shift; member
475 .div_shift = ds, \
497 .div_shift = ds, \
515 .div_shift = ds, \
533 .div_shift = ds, \
573 .div_shift = ds, \
592 .div_shift = ds, \
608 .div_shift = 16, \
707 .div_shift = s, \
722 .div_shift = s, \
[all …]
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| A D | clk-ddr.c | 21 int div_shift; member
94 int div_shift, int div_width, in rockchip_clk_register_ddrclk() argument
129 ddrclk->div_shift = div_shift; in rockchip_clk_register_ddrclk()
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| A D | clk.c | 43 int div_offset, u8 div_shift, u8 div_width, u8 div_flags, in rockchip_clk_register_branch() argument
96 div->shift = div_shift; in rockchip_clk_register_branch()
463 list->div_shift, list->div_width, in rockchip_clk_register_branches()
470 list->div_shift, list->div_width, in rockchip_clk_register_branches()
487 list->mux_flags, list->div_shift, in rockchip_clk_register_branches()
506 list->div_offset, list->div_shift, list->div_width, in rockchip_clk_register_branches()
516 list->div_shift in rockchip_clk_register_branches()
524 list->div_shift, list->div_flags, &ctx->lock); in rockchip_clk_register_branches()
530 list->div_shift, list->div_width, in rockchip_clk_register_branches()
539 list->mux_width, list->div_shift, in rockchip_clk_register_branches()
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| A D | clk-half-divider.c | 163 u8 div_shift, u8 div_width, in rockchip_clk_register_halfdiv() argument
209 div->shift = div_shift; in rockchip_clk_register_halfdiv()
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| /linux/drivers/clk/x86/ |
| A D | clk-cgu.h | 187 u8 div_shift; member
235 .div_shift = _shift, \
275 .div_shift = _shift, \
295 .div_shift = _shift, \
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| A D | clk-cgu.c | 31 lgm_set_clk_val(ctx->membase, list->div_off, list->div_shift, in lgm_clk_register_fixed()
220 u8 shift = list->div_shift; in lgm_clk_register_divider()
278 lgm_set_clk_val(ctx->membase, list->div_off, list->div_shift, in lgm_clk_register_fixed_factor()
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| /linux/drivers/clk/imx/ |
| A D | clk-pllv3.c | 52 u32 div_shift; member
114 u32 div = (readl_relaxed(pll->base) >> pll->div_shift) & pll->div_mask; in clk_pllv3_recalc_rate()
142 val &= ~(pll->div_mask << pll->div_shift); in clk_pllv3_set_rate()
143 val |= (div << pll->div_shift); in clk_pllv3_set_rate()
438 pll->div_shift = 1; in imx_clk_hw_pllv3()
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| /linux/drivers/clk/mediatek/ |
| A D | clk-mtk.h | 185 unsigned char div_shift; member
196 .div_shift = _shift, \
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| A D | clk-mt8167.c | 662 .div_shift = _shift, \
692 .div_shift = _shift, \
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| A D | clk-mtk.c | 292 mcd->flags, base + mcd->div_reg, mcd->div_shift, in mtk_clk_register_dividers()
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| A D | clk-mt8516.c | 472 .div_shift = _shift, \
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| /linux/drivers/clk/ |
| A D | clk-bm1880.c | 120 s8 div_shift; member
152 .div_shift = _div_shift, \
168 .div_shift = -1, \
819 if (clks->div_shift >= 0) { in bm1880_clk_register_composite()
828 div_hws->div.shift = clks->div_shift; in bm1880_clk_register_composite()
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| A D | clk-k210.c | 36 u8 div_shift; member
56 .div_shift = (_shift), \
759 div_val = (reg >> cfg->div_shift) & GENMASK(cfg->div_width - 1, 0); in k210_clk_get_rate()
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| /linux/drivers/clk/at91/ |
| A D | clk-sam9x60-pll.c | 346 (div << core->layout->div_shift) | ena_val); in sam9x60_div_pll_set_div()
367 cdiv = (val & core->layout->div_mask) >> core->layout->div_shift; in sam9x60_div_pll_set()
513 cdiv = (val & core->layout->div_mask) >> core->layout->div_shift; in sam9x60_div_pll_set_rate_chg()
569 cdiv = (val & core.layout->div_mask) >> core.layout->div_shift; in sam9x60_div_pll_notifier_fn()
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| A D | pmc.h | 65 u8 div_shift; member
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| A D | sam9x60.c | 56 .div_shift = 0,
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| A D | sama7g5.c | 81 .div_shift = 0,
89 .div_shift = 12,
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| /linux/drivers/clk/samsung/ |
| A D | clk-s3c2410-dclk.c | 174 int div_shift, int cmp_shift) in s3c24xx_dclk_update_cmp() argument
183 div = ((dclk_con >> div_shift) & DCLKCON_DCLK_DIV_MASK) + 1; in s3c24xx_dclk_update_cmp()
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| /linux/drivers/mfd/ |
| A D | db8500-prcmu.c | 523 u32 div_shift; member
530 .div_shift = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_SHIFT,
535 .div_shift = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_SHIFT,
540 .div_shift = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_SHIFT,
1534 div = ((div & dsiescclk[n].div_mask) >> (dsiescclk[n].div_shift)); in dsiescclk_rate()
1899 val |= (min(div, (u32)255) << dsiescclk[n].div_shift); in set_dsiescclk_rate()
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| /linux/drivers/clk/tegra/ |
| A D | clk-tegra-periph.c | 832 u8 div_shift; member
843 .div_shift = _div_shift,\
967 data->div_shift, 8, 1, data->lock); in init_pllp()
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