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/linux/drivers/clk/tegra/
A Dclk-divider.c27 divider->frac_width, divider->flags); in get_div()
49 div = (reg >> divider->shift) & div_mask(divider); in clk_frac_div_recalc_rate()
51 mul = get_mul(divider); in clk_frac_div_recalc_rate()
92 if (divider->lock) in clk_frac_div_set_rate()
96 val &= ~(div_mask(divider) << divider->shift); in clk_frac_div_set_rate()
111 if (divider->lock) in clk_frac_div_set_rate()
143 divider = kzalloc(sizeof(*divider), GFP_KERNEL); in tegra_clk_register_divider()
144 if (!divider) { in tegra_clk_register_divider()
156 divider->reg = reg; in tegra_clk_register_divider()
160 divider->lock = lock; in tegra_clk_register_divider()
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/linux/drivers/clk/ti/
A Ddivider.c46 if (divider->table) { in _setup_mask()
74 if (divider->table) in _get_div()
96 if (divider->table) in _get_val()
107 val = ti_clk_ll_ops->clk_readl(&divider->reg) >> divider->shift; in ti_clk_divider_recalc_rate()
142 if (divider->table) in _is_valid_div()
265 val &= ~(divider->mask << divider->shift); in ti_clk_divider_set_rate()
269 ti_clk_latch(&divider->reg, divider->latch); in ti_clk_divider_set_rate()
285 val = ti_clk_ll_ops->clk_readl(&divider->reg) >> divider->shift; in clk_divider_save_context()
286 divider->context = val & divider->mask; in clk_divider_save_context()
303 val &= ~(divider->mask << divider->shift); in clk_divider_restore_context()
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A Dclk-dra7-atl.c57 u32 divider; /* Cached divider value */ member
93 cdesc->divider - 1); in atl_clk_enable()
128 return parent_rate / cdesc->divider; in atl_clk_recalc_rate()
134 unsigned divider; in atl_clk_round_rate() local
138 divider = DRA7_ATL_DIVIDER_MASK + 1; in atl_clk_round_rate()
140 return *parent_rate / divider; in atl_clk_round_rate()
147 u32 divider; in atl_clk_set_rate() local
154 if (divider > DRA7_ATL_DIVIDER_MASK) in atl_clk_set_rate()
155 divider = DRA7_ATL_DIVIDER_MASK; in atl_clk_set_rate()
157 cdesc->divider = divider + 1; in atl_clk_set_rate()
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/linux/drivers/clk/qcom/
A Dclk-regmap-divider.c22 struct clk_regmap *clkr = &divider->clkr; in div_round_ro_rate()
25 regmap_read(clkr->regmap, divider->reg, &val); in div_round_ro_rate()
26 val >>= divider->shift; in div_round_ro_rate()
27 val &= BIT(divider->width) - 1; in div_round_ro_rate()
46 struct clk_regmap *clkr = &divider->clkr; in div_set_rate()
53 (BIT(divider->width) - 1) << divider->shift, in div_set_rate()
54 div << divider->shift); in div_set_rate()
61 struct clk_regmap *clkr = &divider->clkr; in div_recalc_rate()
64 regmap_read(clkr->regmap, divider->reg, &div); in div_recalc_rate()
65 div >>= divider->shift; in div_recalc_rate()
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/linux/drivers/clk/mvebu/
A Ddove-divider.c62 divider = dc->divider_table[divider]; in dove_get_divider()
64 return divider; in dove_get_divider()
79 divider = i; in dove_calc_divider()
88 if (set && (divider == 0 || divider >= max)) in dove_calc_divider()
93 divider = 1; in dove_calc_divider()
96 return divider; in dove_calc_divider()
116 int divider; in dove_round_rate() local
119 if (divider < 0) in dove_round_rate()
120 return divider; in dove_round_rate()
135 int divider; in dove_set_clock() local
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/linux/drivers/clk/
A Dclk-divider.c155 val = clk_div_readl(divider) >> divider->shift; in clk_divider_recalc_rate()
159 divider->flags, divider->width); in clk_divider_recalc_rate()
437 val = clk_div_readl(divider) >> divider->shift; in clk_divider_round_rate()
441 divider->width, divider->flags, in clk_divider_round_rate()
446 divider->width, divider->flags); in clk_divider_round_rate()
458 val = clk_div_readl(divider) >> divider->shift; in clk_divider_determine_rate()
496 divider->width, divider->flags); in clk_divider_set_rate()
500 if (divider->lock) in clk_divider_set_rate()
506 val = clk_div_mask(divider->width) << (divider->shift + 16); in clk_divider_set_rate()
509 val &= ~(clk_div_mask(divider->width) << divider->shift); in clk_divider_set_rate()
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A Dclk-milbeaut.c382 val = readl(divider->reg) >> divider->shift; in m10v_clk_divider_recalc_rate()
386 divider->flags, divider->width); in m10v_clk_divider_recalc_rate()
398 val = readl(divider->reg) >> divider->shift; in m10v_clk_divider_round_rate()
402 divider->width, divider->flags, in m10v_clk_divider_round_rate()
407 divider->width, divider->flags); in m10v_clk_divider_round_rate()
420 divider->width, divider->flags); in m10v_clk_divider_set_rate()
424 if (divider->lock) in m10v_clk_divider_set_rate()
427 __acquire(divider->lock); in m10v_clk_divider_set_rate()
429 val = readl(divider->reg); in m10v_clk_divider_set_rate()
430 val &= ~(clk_div_mask(divider->width) << divider->shift); in m10v_clk_divider_set_rate()
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/linux/drivers/clk/rockchip/
A Dclk-half-divider.c28 val = readl(divider->reg) >> divider->shift; in clk_half_divider_recalc_rate()
102 divider->width, in clk_half_divider_round_rate()
103 divider->flags); in clk_half_divider_round_rate()
120 if (divider->lock) in clk_half_divider_set_rate()
123 __acquire(divider->lock); in clk_half_divider_set_rate()
126 val = div_mask(divider->width) << (divider->shift + 16); in clk_half_divider_set_rate()
128 val = readl(divider->reg); in clk_half_divider_set_rate()
129 val &= ~(div_mask(divider->width) << divider->shift); in clk_half_divider_set_rate()
132 writel(val, divider->reg); in clk_half_divider_set_rate()
134 if (divider->lock) in clk_half_divider_set_rate()
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/linux/drivers/clk/imx/
A Dclk-fixup-div.c24 struct clk_divider divider; member
33 return container_of(divider, struct clk_fixup_div, divider); in to_clk_fixup_div()
57 unsigned int divider, value; in clk_fixup_div_set_rate() local
61 divider = parent_rate / rate; in clk_fixup_div_set_rate()
64 value = divider - 1; in clk_fixup_div_set_rate()
110 fixup_div->divider.reg = reg; in imx_clk_hw_fixup_divider()
111 fixup_div->divider.shift = shift; in imx_clk_hw_fixup_divider()
112 fixup_div->divider.width = width; in imx_clk_hw_fixup_divider()
113 fixup_div->divider.lock = &imx_ccm_lock; in imx_clk_hw_fixup_divider()
114 fixup_div->divider.hw.init = &init; in imx_clk_hw_fixup_divider()
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A Dclk-composite-8m.c31 struct clk_divider *divider = to_clk_divider(hw); in imx8m_clk_composite_divider_recalc_rate() local
36 prediv_value = readl(divider->reg) >> divider->shift; in imx8m_clk_composite_divider_recalc_rate()
37 prediv_value &= clk_div_mask(divider->width); in imx8m_clk_composite_divider_recalc_rate()
40 NULL, divider->flags, in imx8m_clk_composite_divider_recalc_rate()
41 divider->width); in imx8m_clk_composite_divider_recalc_rate()
47 divider->flags, PCG_DIV_WIDTH); in imx8m_clk_composite_divider_recalc_rate()
107 spin_lock_irqsave(divider->lock, flags); in imx8m_clk_composite_divider_set_rate()
109 val = readl(divider->reg); in imx8m_clk_composite_divider_set_rate()
110 val &= ~((clk_div_mask(divider->width) << divider->shift) | in imx8m_clk_composite_divider_set_rate()
115 writel(val, divider->reg); in imx8m_clk_composite_divider_set_rate()
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A Dclk-divider-gate.c15 struct clk_divider divider; member
23 return container_of(div, struct clk_divider_gate, divider); in to_clk_divider_gate()
201 div_gate->divider.reg = reg; in imx_clk_hw_divider_gate()
202 div_gate->divider.shift = shift; in imx_clk_hw_divider_gate()
203 div_gate->divider.width = width; in imx_clk_hw_divider_gate()
204 div_gate->divider.lock = lock; in imx_clk_hw_divider_gate()
205 div_gate->divider.table = table; in imx_clk_hw_divider_gate()
206 div_gate->divider.hw.init = &init; in imx_clk_hw_divider_gate()
207 div_gate->divider.flags = CLK_DIVIDER_ONE_BASED | clk_divider_flags; in imx_clk_hw_divider_gate()
213 hw = &div_gate->divider.hw; in imx_clk_hw_divider_gate()
/linux/drivers/clk/mxs/
A Dclk-div.c22 struct clk_divider divider; member
30 struct clk_divider *divider = to_clk_divider(hw); in to_clk_div() local
32 return container_of(divider, struct clk_div, divider); in to_clk_div()
48 return div->ops->round_rate(&div->divider.hw, rate, prate); in clk_div_round_rate()
90 div->divider.reg = reg; in mxs_clk_div()
91 div->divider.shift = shift; in mxs_clk_div()
92 div->divider.width = width; in mxs_clk_div()
93 div->divider.flags = CLK_DIVIDER_ONE_BASED; in mxs_clk_div()
94 div->divider.lock = &mxs_lock; in mxs_clk_div()
95 div->divider.hw.init = &init; in mxs_clk_div()
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/linux/drivers/clk/zynqmp/
A Ddivider.c84 u32 clk_id = divider->clk_id; in zynqmp_clk_divider_recalc_rate()
85 u32 div_type = divider->div_type; in zynqmp_clk_divider_recalc_rate()
100 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) in zynqmp_clk_divider_recalc_rate()
115 struct zynqmp_clk_divider *divider, in zynqmp_get_divider2_val() argument
137 for (div2 = 1; div2 <= divider->max_div;) { in zynqmp_get_divider2_val()
170 u32 clk_id = divider->clk_id; in zynqmp_clk_divider_round_rate()
171 u32 div_type = divider->div_type; in zynqmp_clk_divider_round_rate()
176 if (divider->flags & CLK_DIVIDER_READ_ONLY) { in zynqmp_clk_divider_round_rate()
227 u32 clk_id = divider->clk_id; in zynqmp_clk_divider_set_rate()
228 u32 div_type = divider->div_type; in zynqmp_clk_divider_set_rate()
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/linux/drivers/clk/baikal-t1/
A Dccu-div.c177 unsigned long divider; in ccu_div_var_recalc_rate() local
190 unsigned long divider; in ccu_div_var_calc_divider() local
201 unsigned long divider; in ccu_div_var_round_rate() local
223 divider = 0; in ccu_div_var_set_rate_slow()
225 if (divider == 1 || divider == 2) in ccu_div_var_set_rate_slow()
226 divider = 0; in ccu_div_var_set_rate_slow()
227 else if (divider == 3) in ccu_div_var_set_rate_slow()
228 divider = 4; in ccu_div_var_set_rate_slow()
411 *val = div->divider; in ccu_div_dbgfs_fixed_clkdiv_get()
568 div->divider = div_init->divider; in ccu_div_hw_register()
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/linux/drivers/staging/clocking-wizard/
A Dclk-xlnx-clock-wizard.c126 void __iomem *div_addr = divider->base + divider->offset; in clk_wzrd_recalc_rate()
130 val &= div_mask(divider->width); in clk_wzrd_recalc_rate()
133 divider->flags, divider->width); in clk_wzrd_recalc_rate()
143 void __iomem *div_addr = divider->base + divider->offset; in clk_wzrd_dynamic_reconfig()
145 if (divider->lock) in clk_wzrd_dynamic_reconfig()
148 __acquire(divider->lock); in clk_wzrd_dynamic_reconfig()
175 if (divider->lock) in clk_wzrd_dynamic_reconfig()
178 __release(divider->lock); in clk_wzrd_dynamic_reconfig()
208 void __iomem *div_addr = divider->base + divider->offset; in clk_wzrd_recalc_ratef()
211 div = val & div_mask(divider->width); in clk_wzrd_recalc_ratef()
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/linux/drivers/gpu/drm/i915/display/
A Dintel_cdclk.c614 u32 divider; in vlv_set_cdclk() local
616 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, in vlv_set_cdclk()
622 val |= divider; in vlv_set_cdclk()
1456 u32 divider; in bxt_get_cdclk() local
1475 switch (divider) { in bxt_get_cdclk()
1489 MISSING_CASE(divider); in bxt_get_cdclk()
2766 int divider, fraction; in cnp_rawclk() local
2770 divider = 24000; in cnp_rawclk()
2774 divider = 19000; in cnp_rawclk()
2778 rawclk = CNP_RAWCLK_DIV(divider / 1000); in cnp_rawclk()
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/linux/Documentation/devicetree/bindings/iio/afe/
A Dvoltage-divider.yaml4 $id: http://devicetree.org/schemas/iio/afe/voltage-divider.yaml#
7 title: Voltage divider
13 When an io-channel measures the midpoint of a voltage divider, the
15 of the divider. This binding describes the voltage divider in such
35 const: voltage-divider
48 Resistance R + Rout for the full divider. The io-channel is scaled by
64 * voltage divider (R = 200 Ohms, Rout = 22 Ohms) and fed to an ADC.
79 compatible = "voltage-divider";
/linux/drivers/clk/davinci/
A Dpll.c255 divider = kzalloc(sizeof(*divider), GFP_KERNEL); in davinci_pll_div_register()
256 if (!divider) { in davinci_pll_div_register()
261 divider->reg = reg; in davinci_pll_div_register()
281 kfree(divider); in davinci_pll_div_register()
601 divider = kzalloc(sizeof(*divider), GFP_KERNEL); in davinci_pll_obsclk_register()
602 if (!divider) { in davinci_pll_obsclk_register()
630 kfree(divider); in davinci_pll_obsclk_register()
702 divider = kzalloc(sizeof(*divider), GFP_KERNEL); in davinci_pll_sysclk_register()
703 if (!divider) { in davinci_pll_sysclk_register()
711 divider->flags = 0; in davinci_pll_sysclk_register()
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/linux/Documentation/devicetree/bindings/clock/ti/
A Ddivider.txt1 Binding for TI divider clock
6 register-mapped adjustable clock rate divider that does not gate and has
44 The binding must also provide the register to control the divider and
45 unless the divider array is provided, min and max dividers. Optionally
56 - compatible : shall be "ti,divider-clock" or "ti,composite-divider-clock".
59 - reg : offset for register controlling adjustable divider
64 - ti,bit-shift : number of bits to shift the divider value, defaults to 0
85 compatible = "ti,divider-clock";
94 compatible = "ti,divider-clock";
103 compatible = "ti,composite-divider-clock";
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/linux/Documentation/devicetree/bindings/clock/
A Dxgene.txt37 reset and/or the divider. Either may be omitted, but at least
55 - divider-offset : Offset to the divider CSR register from the divider base.
57 - divider-width : Width of the divider register. Default is 0.
58 - divider-shift : Bit shift of the divider register. Default is 0.
107 divider-offset = <0x238>;
108 divider-width = <0x9>;
109 divider-shift = <0x0>;
125 divider-offset = <0x10>;
126 divider-width = <0x2>;
127 divider-shift = <0x0>;
A Dkeystone-pll.txt4 a divider and a post divider. The additional PLL IPs like ARMPLL, DDRPLL
18 - reg-names : control, multiplier and post-divider. The multiplier and
19 post-divider registers are applicable only for main pll clock
20 - fixed-postdiv : fixed post divider value. If absent, use clkod register bits
29 reg-names = "control", "multiplier", "post-divider";
66 - compatible : shall be "ti,keystone,pll-divider-clock"
70 - bit-mask : arbitrary bitmask for programming the divider
78 compatible = "ti,keystone,pll-divider-clock";
/linux/drivers/media/i2c/cx25840/
A Dcx25840-ir.c148 return DIV_ROUND_CLOSEST((divider + 1) * 1000, in clock_divider_to_ns()
174 (divider + 1) * rollovers); in clock_divider_to_freq()
413 u16 *divider) in txclk_tx_s_carrier() argument
415 *divider = carrier_freq_to_clock_divider(freq); in txclk_tx_s_carrier()
417 return clock_divider_to_carrier_freq(*divider); in txclk_tx_s_carrier()
422 u16 *divider) in rxclk_rx_s_carrier() argument
424 *divider = carrier_freq_to_clock_divider(freq); in rxclk_rx_s_carrier()
426 return clock_divider_to_carrier_freq(*divider); in rxclk_rx_s_carrier()
430 u16 *divider) in txclk_tx_s_max_pulse_width() argument
443 u16 *divider) in rxclk_rx_s_max_pulse_width() argument
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/linux/drivers/clk/x86/
A Dclk-cgu.c142 spin_lock_irqsave(&divider->lock, flags); in lgm_clk_divider_recalc_rate()
143 val = lgm_get_clk_val(divider->membase, divider->reg, in lgm_clk_divider_recalc_rate()
144 divider->shift, divider->width); in lgm_clk_divider_recalc_rate()
145 spin_unlock_irqrestore(&divider->lock, flags); in lgm_clk_divider_recalc_rate()
148 divider->flags, divider->width); in lgm_clk_divider_recalc_rate()
158 divider->width, divider->flags); in lgm_clk_divider_round_rate()
170 divider->width, divider->flags); in lgm_clk_divider_set_rate()
174 spin_lock_irqsave(&divider->lock, flags); in lgm_clk_divider_set_rate()
175 lgm_set_clk_val(divider->membase, divider->reg, in lgm_clk_divider_set_rate()
176 divider->shift, divider->width, value); in lgm_clk_divider_set_rate()
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/linux/drivers/i2c/busses/
A Di2c-bcm2835.c88 u32 divider = DIV_ROUND_UP(parent_rate, rate); in clk_bcm2835_i2c_calc_divider() local
95 if (divider & 1) in clk_bcm2835_i2c_calc_divider()
96 divider++; in clk_bcm2835_i2c_calc_divider()
97 if ((divider < BCM2835_I2C_CDIV_MIN) || in clk_bcm2835_i2c_calc_divider()
98 (divider > BCM2835_I2C_CDIV_MAX)) in clk_bcm2835_i2c_calc_divider()
101 return divider; in clk_bcm2835_i2c_calc_divider()
111 if (divider == -EINVAL) in clk_bcm2835_i2c_set_rate()
121 fedl = max(divider / 16, 1u); in clk_bcm2835_i2c_set_rate()
127 redl = max(divider / 4, 1u); in clk_bcm2835_i2c_set_rate()
140 return DIV_ROUND_UP(*parent_rate, divider); in clk_bcm2835_i2c_round_rate()
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/linux/arch/arm/boot/dts/
A Ddra7xx-clocks.dtsi211 compatible = "ti,divider-clock";
222 compatible = "ti,divider-clock";
231 compatible = "ti,divider-clock";
242 compatible = "ti,divider-clock";
274 compatible = "ti,divider-clock";
300 compatible = "ti,divider-clock";
344 compatible = "ti,divider-clock";
382 compatible = "ti,divider-clock";
420 compatible = "ti,divider-clock";
433 compatible = "ti,divider-clock";
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