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Searched refs:dp_phy (Results 1 – 19 of 19) sorted by relevance

/linux/drivers/gpu/drm/i915/display/
A Dintel_dp_link_training.c43 if (dp_phy == DP_PHY_DPRX) in intel_dp_phy_name()
52 enum drm_dp_phy dp_phy) in intel_dp_lttpr_phy_caps() argument
58 enum drm_dp_phy dp_phy) in intel_dp_read_lttpr_phy_caps() argument
366 enum drm_dp_phy dp_phy, in intel_dp_get_lane_adjust_train() argument
404 enum drm_dp_phy dp_phy, in intel_dp_get_adjust_train() argument
447 enum drm_dp_phy dp_phy, in intel_dp_set_link_train() argument
528 enum drm_dp_phy dp_phy) in intel_dp_set_signal_levels() argument
559 enum drm_dp_phy dp_phy, in intel_dp_reset_link_train() argument
689 if (dp_phy == DP_PHY_DPRX) in intel_dp_link_training_clock_recovery_delay()
948 dp_phy); in intel_dp_link_training_channel_equalization()
[all …]
A Dintel_dp_link_training.h18 enum drm_dp_phy dp_phy,
22 enum drm_dp_phy dp_phy,
26 enum drm_dp_phy dp_phy);
/linux/include/drm/
A Ddrm_dp_helper.h1366 #define DP_LTTPR_BASE(dp_phy) \ argument
1368 ((dp_phy) - DP_PHY_LTTPR1))
1370 #define DP_LTTPR_REG(dp_phy, lttpr1_reg) \ argument
1393 #define DP_LANE0_1_STATUS_PHY_REPEATER(dp_phy) \ argument
1408 #define DP_FEC_BASE(dp_phy) \ argument
1410 ((dp_phy) - DP_PHY_LTTPR1)))
1412 #define DP_FEC_REG(dp_phy, fec1_reg) \ argument
1416 #define DP_FEC_STATUS_PHY_REPEATER(dp_phy) \ argument
1417 DP_FEC_REG(dp_phy, DP_FEC_STATUS_PHY_REPEATER1)
2066 enum drm_dp_phy dp_phy,
[all …]
/linux/Documentation/devicetree/bindings/display/msm/
A Ddp-controller.yaml128 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
130 phys = <&dp_phy>;
/linux/Documentation/devicetree/bindings/clock/
A Dqcom,sc7180-dispcc.yaml74 <&dp_phy 0>,
75 <&dp_phy 1>;
A Dqcom,sc7280-dispcc.yaml78 <&dp_phy 0>,
79 <&dp_phy 1>,
A Dqcom,dispcc-sm8x50.yaml92 <&dp_phy 0>,
93 <&dp_phy 1>;
A Dqcom,sdm845-dispcc.yaml86 <&dp_phy 0>,
87 <&dp_phy 1>;
/linux/Documentation/devicetree/bindings/display/bridge/
A Danalogix_dp.txt49 phys = <&dp_phy>;
A Dcdns,mhdp8546.yaml140 phys = <&dp_phy>;
/linux/Documentation/devicetree/bindings/display/rockchip/
A Danalogix_dp-rockchip.txt52 phys = <&dp_phy>;
/linux/Documentation/devicetree/bindings/display/exynos/
A Dexynos_dp.txt84 phys = <&dp_phy>;
/linux/drivers/gpu/drm/
A Ddrm_dp_helper.c449 enum drm_dp_phy dp_phy, in drm_dp_dpcd_read_phy_link_status() argument
454 if (dp_phy == DP_PHY_DPRX) { in drm_dp_dpcd_read_phy_link_status()
469 DP_LANE0_1_STATUS_PHY_REPEATER(dp_phy), in drm_dp_dpcd_read_phy_link_status()
2239 enum drm_dp_phy dp_phy, in drm_dp_read_lttpr_phy_caps() argument
2245 DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy), in drm_dp_read_lttpr_phy_caps()
/linux/arch/arm64/boot/dts/qcom/
A Dsc7180.dtsi2713 dp_phy: dp-phy@88ea200 { label
3106 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
3107 phys = <&dp_phy>;
3164 <&dp_phy 0>,
3165 <&dp_phy 1>;
A Dsm6350.dtsi557 dp_phy: dp-phy@88ea200 { label
A Dsm8250.dtsi2293 dp_phy: dp-phy@88ea200 { label
2850 <&dp_phy 0>,
2851 <&dp_phy 1>;
A Dsc7280.dtsi2525 dp_phy: dp-phy@88ea200 { label
/linux/arch/arm/boot/dts/
A Dexynos5250.dtsi823 dp_phy: video-phy { label
1140 phys = <&dp_phy>;
A Dexynos5420.dtsi598 dp_phy: dp-video-phy { label
1226 phys = <&dp_phy>;

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